Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2002-08-28
2004-12-28
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S696000, C257S735000, C257S724000, C257S786000
Reexamination Certificate
active
06836009
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims foreign priority benefits of Singapore Application No. 200204788-4 filed Aug. 8, 2002, the entirety of which is incorporated herein by reference.
BACKGROUND
The present invention relates to packaged microelectronic components and methods for assembling the same. In particular, aspects of the invention relate to leaded microelectronic component packages and to stacked microelectronic component assemblies.
Semiconductor chips or dies are typically encapsulated in a package which protects the chips from the surrounding environment. The packages typically include leads or other connection points which allow the encapsulated chip to be electrically coupled to another microelectronic component. Leaded packages include a semiconductor chip bonded to a lead frame either seated on a die paddle or directly to the leads in a leads-over-chip attachment. The contacts pads on the semiconductor die are then electrically connected to the chip, e.g., by wirebonding. The connected lead frame and chip may then be encapsulated in an encapsulant to form a complete microelectronic component package. In most common applications, the leads extend out from the mold compound, allowing the chip to be electrically accessed. Typically, the leads extend laterally outwardly in a flat array which is part of a lead frame. This lead frame may be trimmed and formed into a desired configuration.
One technique for manufacturing microelectronic components is the “flip-chip” technique. In this approach, a microelectronic component, such as a semiconductor chip or die, includes a plurality of bond pads or other electrical contacts arranged in an array and each of these bond pads includes a solder ball. This array of solder balls, referred as a ball grid array (“BGA”), allows the microelectronic component to be attached to another element of a microelectronic component assembly by contacting the array of solder balls to a mating array of terminals carried by the other element.
While BGA chips or packages facilitate ready interconnection of microelectronic components, omitting the leads employed in a conventional leaded package sacrifices certain advantages provided by the leads. Some have proposed techniques for combining the advantages of lead frame packages with a BGA package. For example, U.S. Pat. No. 5,847,455 (Manteghi) and U.S. Pat. No. 5,663,593 (Mostafazadeh et al.), the entirety of each of which is incorporated herein by reference, are each directed to microelectronic component packages which include both electrical leads and ball grid arrays to allow the package to be mounted in a flip-chip fashion. These microelectronic component packages are formed by attaching a microelectronic component to a lead frame die paddle, wirebonding the die to the leads of the lead frame, and encapsulating the microelectronic component and the leads in an encapsulant. A solder mask is applied to the face of the lead frame facing away from the microelectronic component and holes are formed in the solder mask to expose a surface of the underlying lead. Solder balls can be disposed within the holes in the encapsulant to form a ball grid array on the package.
U.S. Pat. No. 6,028,356 (Kimura) suggests a similar approach, but proposes eliminating the solder mask. Instead, the package is encapsulated in two steps. In the first step, the microelectronic component and the side of the leads facing the microelectronic component are encapsulated; in the second step, the other side of the leads are encapsulated. The encapsulant mold used in the second step includes bumps which contact the lead frame, producing dimples that allow the leads to be electrically accessed. Solder balls may then be created in the dimples.
U.S. Pat. No. 5,866,939, the entirety of which is incorporated herein by reference, proposes another microelectronic component package which employs both leads and a BGA. The leads of the lead frame are bent, causing the ends to terminate at the surface of the package. These lead ends define an array of contacts which can bear solder balls in a ball grid array. These leads vary in length, which can compromise signal transmission, especially in higher-speed, higher-frequency devices. In addition, this approach may result in a weaker structure than may be obtained with leads extending across more of the width of the package as these leads can add additional structural reinforcement to the microelectronic component package.
Each of these references is also limited to a BGA attachment to one other microelectronic component. Although the leads are incorporated in the microelectronic component package for ease of manufacture, the leads do not extend outwardly beyond the periphery of the package to permit the leads to be electrically coupled to a substrate in a manner conventional for leaded packages. Consequently, the microelectronic components in these proposed packages can be electrically connected to other components only via the solder balls of the ball grid array. The leads in a conventional leaded package not only facilitate electrical connection to a substrate or other microelectronic component, but also provide a thermal pathway to conduct heat away from the package during operation. The lead frame/BGA design suggested in these four references sacrifice this advantage, as well.
One increasingly popular technique for maximizing device density on a substrate is to stack microelectronic devices on top of one another. Stacking just one device on top of a lower device can effectively double the circuitry within a given footprint; stacking additional devices can further increase the circuit density. In forming a stacked microelectronic device assembly, it is necessary to provide electrical connections between the underlying substrate and the upper component(s). Unfortunately, the packages proposed in these four patents only provide electrical connections on a single face of the package. This effectively prevents these microelectronic component packages from being stacked atop one another in a stacked component assembly. In particular, it may be possible to use one of these microelectronic component packages as the upper most package of a stacked microelectronic component assembly, but these microelectronic component packages would have marginal utility as the lower packages in a stacked assembly.
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Koon Eng Meow
Leng Ser Bok
Poo Chia Yong
Waf Low Siu
Wei Zhou
Jackson Jerome
Micro)n Technology, Inc.
Perkins Coie LLP
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