Packaged integrated circuits and methods of producing thereof

Details Packaged integrated circuits and methods of producing thereof Packaged integrated circuits and methods of producing thereof

2001-01-11

2003-09-23

Ho, Hoai (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S787000, C257S627000, C438S106000

Reexamination Certificate

active

06624505

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated packaging, packaged integrated circuits and methods of producing packaged integrated circuits.
BACKGROUND OF THE INVENTION
Various types of packaged integrated circuits are known in the prior art. The following patents and published patent applications of the present inventor and the references cited therein are believed to represent the state of the art:
U.S. Pat. Nos. 4,551,629; 4,764,846; 4,794,092; 4,862,249; 4,984,358; 5,104,820; 5,126,286; 5,266,833; 5,546,654; 5,567,657; 5,612,570; 5,657,206; 5,661,087; 5,675,180; 5,703,400; 5,837,566; 5,849,623; 5,857,858; 5,859,475; 5,869,353; 5,888,884; 5,891,761; 5,900,674; 5,938,45; 5,985,695; 6,002,163; 6,046,410; 6,080,596; 6,092,280; 6,098,278; 6,124,637; 6,134,118.
EP 490739 A1; JP 63-166710
WO 85/02283; WO 89/04113; WO 95/19645
The disclosures in the following publications:
“Three Dimensional Hybrid Wafer Scale Integration Using the GE High Density Interconnect Technology” by R. J. Wojnarowski, R. A Filliion, B. Gorowitz and R. Saia of General Electric Company, Corporate Research & Development, P.O. Box 8, Schenectady, N.Y. 12301, USA, International Conference on Wafer Scale Integration, 1993.
“M-DENSUS”, Dense-Pac Microsystems, Inc., Semiconductor International, December 1997, p. 50;
“Introduction to Cubic Memory, Inc.” Cubic Memory Incorporated, 27 Janis Way, Scotts Valley, Calif. 95066, USA;
“A Highly Integrated Memory Subsystem for the Smaller Wireless Devices” Intel(r) Stacked-CSP, Intel Corporation, January 2000;
“Product Construction Analysis (Stack CSP)”, Sung-Fei Wang, ASE, R & D Group, Taiwan, 1999;
“Four Semiconductor Manufacturers Agree to Unified Specifications for Stacked Chip Scale Packages”, Mitsubishi Semiconductors, Mitsubishi Electronics America, Inc., 1050 East Arques Avenue, Sunnyvale, Calif. 94086, USA;
“Assembly & Packaging, John Baliga, Technology News, Semiconductor International, December 1999;
“<6 mils Wafer Thickness Solution (DBG Technology)”, Sung-Fei Wang, ASE, R & D Group, Taiwan, 1999;
“Memory Modules Increase Density”, DensePac MicroSystems, Garden Grove, Calif., USA, Electronics Packaging and Production, p. 24, November 1994;
“First Three-Chip Staked CSP Developed”, Semiconductor International, January 2000, p. 22;
“High-Density Packaging: The Next Interconnect Challenge”, Semiconductor International, February 2000, pp. 91-100;
“3-D IC Packaging”, Semiconductor International, p. 20, May 1998;
“High Density Pixel Detector Module Using Flip Chip and Thin Film Technology” J. Wolf, P. Gerlach, E. Beyne, M. Topper, L. Dietrich, K. H. Becks, N. Wermes, O. Ehrmann and H. Reichl, International System Packaging Symposium, January 1999, San Diego;
“Copper Wafer Bonding”, A. Fan, A. Rahman and R. Rief, Electrochemical and Solid State Letters, 2(10), pp. 534-536, 1999;
“Front-End 3-D Packaging”, J. Baliga, Semiconductor International, December 1999, p 52,
are also believed to represent the state of the art.
SUMMARY OF THE INVENTION
The present invention seeks to provide improved packaged integrated circuits and methods for producing same.
There is thus provided in accordance with a preferred embodiment of the present invention a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.
Further in accordance with a preferred embodiment of the present invention the package is a chip-scale package.
Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is partially transparent to infra-red radiation.
There is also provided in accordance with another preferred embodiment of the present invention a packaged integrated circuit assembly including a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface and at least one additional electrical circuit element mounted onto and supported by the second planar surface and electrically coupled to at least one of the plurality of electrical contacts extending therealong.
Further in accordance with a preferred embodiment of the present invention the additional electrical circuit element includes an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
Still further in accordance with a preferred embodiment of the present invention the package is a chip-scale package.
There is further provided in accordance with a preferred embodiment of the present invention a method for producing packaged integrated circuits. The method includes producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, providing wafer scale packaging enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane, forming on the wafer scale packaging a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface and separating the integrated circuit substrate in the wafer scale packaging into a plurality of individual chip packages.
Further in accordance with a preferred embodiment of the present invention the plurality of individual chip packages are chip scale packages.
Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
There is also provided in accordance with yet another preferred embodiment of the present invention a method for producing packaged integrated circuit assemblies. The method includes producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, providing wafer scale packaging enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane, forming on the wafer scale packaging a plurality of electrical contacts, each connected to the electrical circuitry, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts

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