Packaged integrated circuit with MLP leadframe and method of...

Details Packaged integrated circuit with MLP leadframe and method of... Packaged integrated circuit with MLP leadframe and method of...

2007-07-10

2007-07-10

Owens, Douglas W. (Department: 2821)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S690000, C257S701000

Reexamination Certificate

active

10847955

ABSTRACT:
A packaged integrated circuit having a die with multiple transistors selected from the group consisting of multiple logic, linear and analog linear transistors is provided. The die is attached to a die pad with one or more peripheral leads physically isolated from the die pad, one or more leads integrally connected to the die pad, bond wires, and an encapsulant-formed package body. A lip formed by a vertically recessed lower surface is present on two opposing sides and one end of each physically isolated lead, but not on the surfaces of the integrally connected lead(s). Manufacturing the package includes: providing a leadframe having the die pad and leads connected to a frame; mounting the die to the die pad; electrically connecting, with bond wires, the die to the physically isolated lead(s), but not to the integrally connected lead(s); applying an encapsulant to the leadframe that underfills the lips to lock the physically isolated leads in place; and cutting the leads and die pad from the frame.

REFERENCES:
patent: 4998160 (1991-03-01), Dunn
patent: 5703396 (1997-12-01), Kurihara
patent: 6143981 (2000-11-01), Glenn
patent: 6281568 (2001-08-01), Glenn et al.
patent: 6433277 (2002-08-01), Glenn
patent: 6455356 (2002-09-01), Glenn et al.
patent: 6630728 (2003-10-01), Glenn
patent: 6903448 (2005-06-01), Sutardja et al.

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