Packaged integrated circuit with in-cavity decoupling capacitors

Details Packaged integrated circuit with in-cavity decoupling capacitors Packaged integrated circuit with in-cavity decoupling capacitors

1990-09-24

1992-04-07

James, Andrew J.

357 74, H01L 2702, H01L 2302, H01L 2312

Patent

active

051032830

ABSTRACT:
An integrated circuit package is disclosed which has decoupling capacitors mounted within the cavity. A first embodiment has a thin-film capacitor mounted to the die attach of the header, with a first wire bond connecting the top surface to a lead finger of the header, and with a second wire bond connecting the top surface to the semiconductor chip mounted in the package. A second embodiment allows for decoupling of the power supply to a reference voltage other than that of the substrate, by providing a stacked capacitor where the top capacitor has a smaller cross-sectional area than the lower capacitor. Bond wires connect the top surface of the top capacitor to a first power supply lead, such as V.sub.cc, and to the V.sub.cc bond pad of the chip. The top surface of the lower capacitor, and consequently the lower surface of the top capacitor, are connected by bond wires to the reference supply (V.sub.ss) lead of the package and bond pad of the chip.

REFERENCES:
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patent: 3501832 (1970-03-01), Iwata et al.
patent: 3784884 (1974-01-01), Zoroglu
patent: 3838443 (1974-09-01), Laighton
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patent: 4451845 (1984-05-01), Philofsky et al.
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