Packaged integrated circuit and method therefor

Details Packaged integrated circuit and method therefor Packaged integrated circuit and method therefor

2001-12-11

2003-09-09

Talbott, David L. (Department: 2827)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S261000, C174S050510, C361S760000, C361S777000, C361S783000, C257S787000

Reexamination Certificate

active

06617524

ABSTRACT:

FIELD OF THE INVENTION
This relates to packaged semiconductors and more particularly to packaged integrated circuits with encapsulants.
BACKGROUND OF THE INVENTION
When packaging integrated circuits in a plastic ball grid array (PBGA) a mold filling process is typically performed to encapsulate the integrated circuit in order to protect the device from environmental damage. To perform the encapsulation, a cavity is placed over a semiconductor die, which is over a packaging substrate, and an encapsulant material is flowed over the semiconductor die and under the cavity. However, this process often results in the encapsulant flowing outside the area under the cavity (bleeding) due to a gap between the package substrate and the bottom edge of the cavity caused by the presence of traces (metal lines) on the package substrate. This bleeding decreases the quality of the resulting package and can potentially be a reliability issue for the package and the encapsulation equipment. In addition, the bleeding is aesthetically undesirable. Thus, additional subsequent cleaning process steps to remove the bleeded material from the package substrate and the encapsulation equipment are performed.
One way to mitigate bleeding is to apply a large pressure to the top and bottom surfaces of the semiconductor package so that the size of the gap between the package substrate and the cavity is minimized. This large pressure results in cracking of the solder resist, which is a protective layer formed over the integrated circuit and traces. Solder resist cracking can result in decreased reliability of the device by making the package substrate prone to corrosion, for example.
In order to decrease solder resist cracking and allow for a large pressure to be applied during encapsulant formation, dummy traces
10
have been formed on a package substrate
5
, as shown in FIG.
1
. Bond pads
30
on an integrated circuit
20
are connected to electrical traces
50
by wire bonds
40
and bond fingers
45
. The electrical traces
50
include a bond connection
12
, a signal portion
15
and a plating portion
17
. The dummy traces
10
are orthogonal to an edge of the package substrate
5
and/or parallel to the plating portion
17
. The dummy traces
10
are not electrically connected to the integrated circuit
20
. One problem with using dummy traces
10
is that they are not sufficient for preventing fine filler encapsulant material from bleeding, which is being used as the industry moves to fine pitch wire bonding, meaning the distance between the bond pads
30
is decreased to less than approximately 60 microns. For fine pitch wire bonding, smaller filler is needed in the encapsulant material to reduce wire sweep. (Wire sweep is the touching or shorting of adjacent wires.) Gaps between the encapsulant dummy traces
10
are not sufficient for blocking particles, especially those used in fine filler encapsulant materials. Therefore, a need exists in order to prevent bleeding when using fine filler material for fine pitch packages.


REFERENCES:
patent: 5460767 (1995-10-01), Sanftleben et al.
patent: 5737191 (1998-04-01), Horiuchi et al.
patent: 5859475 (1999-01-01), Freyman et al.
patent: 5907190 (1999-05-01), Ishikawa et al.
patent: 6365979 (2002-04-01), Miyajima
patent: 4018399 (1992-01-01), None
patent: 05315393 (1993-11-01), None

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