Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-06-23
2002-03-19
Paladini, Albert W. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000, C174S261000, C174S262000, C361S760000, C361S762000, C361S794000, C361S783000, C257S738000
Reexamination Certificate
active
06359234
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a package substrate for mounting a semiconductor chip and a semiconductor device including the package substrate.
2. Description of the Related Art
In general, a semiconductor chip is used as a semiconductor device with the chip mounted on a package substrate in consideration of the use environment, the ability of mounting or the like. There are various types of packages in accordance with the size or the number of terminals of the semiconductor chip. In the case of a package with many terminals for example, use is sometimes made of a BGA (Ball Grid Array) type in which terminals are arranged in grid form on the lower surface of a package, an LGA (Land Grid Array) type or the like.
With reference to
FIG. 1
, an example of such a package substrate and semiconductor device is explained. In semiconductor device
101
, semiconductor chip
102
having a large number of circuit elements
102
a
of various types (only one of them is shown in
FIG. 1
) is mounted on package substrate
103
. Package substrate
103
has a rectangular opening formed in its central portion in which semiconductor chip
102
is placed. In this case, package substrate
103
and semiconductor chip
102
are supported by heat spreader
107
disposed on their back. Package substrate
103
and semiconductor chip
102
are fixed to heat spreader
107
with adhesive layers
108
and
109
.
Package substrate
103
has a plurality of solder balls
106
formed on its front surface which serve as outer bumps for connection to another circuit device
150
. Package substrate
103
has wiring layers on its surface and interior on which any one of signal wiring
134
, electric power line
135
and ground line
136
is formed. Signal wiring
134
, electric power line
135
and ground line
136
are hereinafter collectively referred to as “wiring
133
”. Each wiring (signal wiring
134
, power line
135
or ground line
136
) is connected to any one of solder balls
106
. On the other hand, terminal
102
b
on a surface of semiconductor chip
102
is electrically connected to any one of wirings
134
,
135
, or
136
through bonding wire
104
. Semiconductor chip
102
and bonding wire
104
are protected by resin portion
105
.
The use of a large number of terminals
102
b
in semiconductor chip
102
causes package substrate
103
to be multi-layered. Specifically, package substrate
103
includes on its surface and inside, a plurality of wiring layers (seven layers in
FIG. 1
) with insulator layers
131
sandwiched therebetween. In this case, the connection between different wiring layers is made via through hole wire
139
on the inner wall of through hole
137
. Formed on the front and back of package substrate
103
at positions corresponding to through hole
137
are through hole lands
138
for electrical conduction to through hole wire
139
. Through hole lands
138
are formed in view of the accuracy of through hole forming steps, and have a required minimum size which is typically slightly larger than the diameter of through hole
137
. In a current standard design rule, the arrangement pitch of solder balls
106
is 1.27 mm. The arrangement pitch of the through holes in this semiconductor device
101
is 1.27 mm to accord with that of solder balls
106
. Accordingly, an inside diameter Ø of the through hole is 0.3 mm, and an outside diameter Ø of the through hole land is 0.55 mm.
The provision of signal wiring on each of a plurality of adjacent wiring layers may have a mutual effect among the signal wiring, causing signal disturbances. To avoid this, both of the wiring layers adjacent to the wiring layer with signal wiring
134
include electric power line
135
or ground line
136
without fail. Signal wiring
134
is formed in a predetermined pattern such that the length between the pad portion to which wiring
104
is connected and solder ball
106
is as uniform and short as possible over the entire semiconductor device
101
. In contrast, electric power line
135
and ground line
136
are formed in a plane or mesh configuration over the entire surfaces of their wiring layers. Such a semiconductor device is disclosed, for example, in Japanese Patent Laid-open No.109924/93 and Japanese Patent Laid-open No.23598/89.
In general, when a plurality of circuits are interconnected, to match the impedance between the respective circuits is needed for preventing reflection of signals and the like. This applies to a semiconductor chip and a package substrate in a semiconductor device. In recent years, a lower impedance is required in the package substrate with improvement in operating frequency of various types of semiconductor devices. Currently, since the access speed to memories is low as compared with the operation speed of processors, the access speed to the memories interferes with the improvement in the processing speed of computers. While various techniques have been developed for providing a faster access speed to the memories, the package substrate having such a fast memory must have an impedance value significantly lower than before. For example, the impedance must be reduced to the order of 28 &OHgr; in a DRDRAM (Direct Rambus Dynamic Random Access Memory) operating at 400 MHz.
For reducing the impedance of the package substrate, it is contemplated to increase the width between wirings. This is, however, undesirable because it invokes a drop in a wiring density. Especially in a package with a large number of pins, a wiring design is extremely difficult. In addition, this method has little effect of reducing the impedance. For example, with a multi-layer substrate using organic interlayer insulator layers with a relative dielectric constant of 4.7, only a 10% reduction in characteristic impedance is obtained even when the width between wirings is increased 50%.
As an alternative to reducing the impedance, it is also contemplated to decrease the interval between the signal wiring layer and the wiring layer at a fixed electrical potential (power layer, ground layer) in the package substrate, i.e., the thickness of the insulator layer. However, an indiscriminate reduction in thickness of the insulator layer makes the dimension (thickness) of the entire semiconductor device different from that of a conventional device. This is not desirable because the dimension of the semiconductor device is standardized to some extent, and a deviation from the standard requires redesign of the other parts. In general, the size, shape or the like of the entire semiconductor device is changed only when significant progress is made in the technology level or contents of the semiconductor device, or the like. Even when it is possible to manufacture a semiconductor chip having the same circuits as before but in a smaller size than before with the advance of its manufacturing technology, the same size and shape as before are often employed for the entire semiconductor device. Therefore, it is required to minimize the possibility that the dimension of the entire semiconductor device is different from a conventional device due to the package substrate.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a package substrate with a low impedance and a semiconductor device including the same.
To solve the aforementioned problems, the package substrate according to the present invention is mounted on an external device with a semiconductor chip having circuit elements and terminals being placed thereon to connect the circuit elements with the external device. The package substrate comprises a plurality of mounting terminals to be mounted on the external device, a plurality of signal wirings provided corresponding to the mounting terminals, a fixed electric potential conductor, and one or more opposed conductor.
The signal wiring connects the terminals of a semiconductor chip to be mounted to the mounting terminals. The fixed electrical potential conductor is maintained at a constant electrical potential when mounted on the e
Hayes, Soloway, Hennessey Grossman & Hage, P.C.
NEC Corporation
Paladini Albert W.
Patel I B
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