Package structure with two solder arrays

Details Package structure with two solder arrays Package structure with two solder arrays

2006-05-09

2006-05-09

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S778000

Reexamination Certificate

active

07042088

ABSTRACT:
The present invention includes a semiconductor package that forms the solder array joints on the die surface and corresponding BGA substrate and PCB respectively. The life times of array solder joints are increased through the use of two sets of array joints. The top array comprises a plurality of high melting solder joints and a plurality of low melting solder joints, while the bottom array comprises a plurality of high melting solder joints only. The reflow temperature of SMT assembly is between the aforementioned high melting point and low melting point of solder joints. In addition, each solder joint comprises a flat surface at its front edge.

REFERENCES:
patent: 5569960 (1996-10-01), Kumazawa et al.
patent: 5598036 (1997-01-01), Ho
patent: 5907187 (1999-05-01), Koiwa et al.
patent: 5956606 (1999-09-01), Burnette
patent: 6455785 (2002-09-01), Sakurai et al.
patent: 6657124 (2003-12-01), Ho
patent: 2002/0079577 (2002-06-01), Ho

Affiliated with

Also associated with

Rating

Package structure with two solder arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Package structure with two solder arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Package structure with two solder arrays will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3645215