Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2000-08-25
2002-12-17
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S723000, C257S737000, C257S697000
Reexamination Certificate
active
06495910
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an IC (integrated circuits) package, particularly to an improvement on an IC package of type BGA (ball grid array).
BACKGROUND OF THE INVENTION
FIG. 1
shows a conventional IC package
1
having solder ball
11
to connect external circuits or apparatus. Limited by the height of the solder ball
11
, the bottom chip
16
(the chip located on a selected surface of substrate where at least a solder ball is also located on the selected surface) supported by substrate
12
must be very thin, resulting in problems that such a thin chip tends to rupture during fabricating process and the fabricating process incurs cost of back grinding of the chip. To overcome the problems inherent in conventional IC packages, solder ball
11
must be enlarged to raise its height, thereby the ball pitch of the solder ball and the size of substrate
12
will have to be augmented, resulting in bigger size of the entire IC package and higher cost of the substrate/package.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an IC package accommodating at least a thicker chip, in order to significantly improve, without need of bigger size of chip carrier or the whole IC package, the failure rate of packaging chips resulting from the thinness of the chips being packaged.
It is therefore another object of the present invention to provide an IC package accommodating at least a thicker chip, in order to significantly reduce or eliminate cost of back grinding of the chips to be packaged.
The present invention is characterized by replacing solder balls with cylindrical terminals in an IC package where at least a chip is located on the same side of the substrate of the IC package as the solder balls are.
Although U.S. Pat. No. 5468995 also adopted cylindrical terminals for an IC package's outward connection, its object is to provide a solution to the problem of thermally induced stress inherent in IC package connection processes such as the connection between the IC package and a printed wiring board, and it disclosure is not related to the objects of the present invention. Furthermore the prior art was to suit an IC package where no chip is located on the same side of substrate as its cylindrical terminals are, and suggested no advantage of either abridging cost of back grinding of a chip or reducing the failure rate resulting from the thinness of a chip being packaged, therefore it is obvious that the present invention and the prior art are significantly different.
A basic structure of the IC package suggested by the present invention may comprise:
a carrier (such as a substrate or any object capable of supporting at least a semiconductor unit and providing electrical connection) including a first surface that comprises at least a semiconductor connection zone and at least a terminal connection zone;
at least a semiconductor unit (such as a flip chip or any type of chip) attached to the semiconductor connection zone;
and at least a cylindrical terminal attached to the terminal connection zone, and electrically connected to the semiconductor unit via the carrier, wherein the length of the cylindrical terminal is larger than the maximum width of the cross section of the cylindrical terminal. Another aspect of the IC package based on the present invention may comprise:
a sheet of carrier including a first surface;
at least a semiconductor unit;
at least a cylindrical terminal; and
a connection system for the semiconductor unit and the cylindrical terminal to respectively connect different portions of the first surface, and for the electrical connection between the semiconductor unit and the cylindrical terminal.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which:
REFERENCES:
patent: 5468995 (1995-11-01), Higgins, III
patent: 5541450 (1996-07-01), Jones
patent: 5550403 (1996-08-01), Carichner
patent: 5977640 (1999-11-01), Bertin et al.
patent: 6081028 (2000-06-01), Ettehadieh et al.
patent: 6235996 (2001-05-01), Farooq
patent: 6259163 (2001-07-01), Ohuchi
patent: 405055450 (1993-03-01), None
Chaudhuri Olik
Ha Nathan W.
Klarquist & Sparkman, LLP
Siliconware Precision Industries Co. Ltd.
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