Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2002-10-30
2004-08-31
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S126000, C438S974000
Reexamination Certificate
active
06784020
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to a packaged structure and method for making this structure, and more specifically to a package for devices of microelectronics, optoelectronics, microelectromechanical systems, micro-fluidic systems, micro-total-analysis-systems, bio-chip and micro-opto-electro-mechanical systems.
BACKGROUND OF THE INVENTION
As there is a tendency that the products are demanded to be lighter, smaller, and portable, the R&D trend of semiconductor, microelectronics, electronics and relative devices is toward miniaturization, higher integration, faster operation speed, and lower power consumption. Thus the packaging technology is required to provide devices and components to meet this trend. Among the packaging technologies, the wafer-level chip size packaging (WLCSP) or wafer-level chip scale packaging (WLCSP) is rather promising technology for fulfilling the miniaturization purpose, because the packaged CSP device size is only about 25% larger than the bare die size.
Due to the development of trend of aforementioned devices, the number of signal I/O (inputs and outputs) of device is increased, the density of interconnection is increased, and the line width of interconnection is reduced. Therefore, the surface mount technology (SMT) is developed in order to solve these problems. Such miniaturizing developments are developed from SOP, SOJ, SSOP, and to TSOP, and from QFP, LQFP, and to TQFP, etc. As the amount of the I/Os is keeping growth, the packaging size will be enlarged, and it is accompanied with many problems, such that non-wetting of soldering balls or the deformation/warpage of substrate. Reducing the packaged size as small as possible may solve these problems. Besides, the arrangement of I/Os location is moving from peripheral site only to all surface of the packaged device, it means there is more area to allocate the I/Os. The chip scale package (CSP) actually realizes these ideas.
Presently, there are over 50 kinds of chip-scale-package (CSP) products disclosed by over 16 semiconductor companies in the world. These CSPs are classified into four types base on the design concepts and package structures.
(1) Leadframe based CSPs: a package design that follows the concept of the LOC (lead on chip), of which the connection between the interposer and the dies is accomplished by wiring, and the area is reduced continuously until the size is achieved at the definition range of the CSP.
(2) CSPs with Rigid Substrate: there is a rigid substrate applied in between the bare die and the package housing structure, and it is used as a carrier; the material thereof mostly is a ceramics substrate or a rigid printed circuit board of polymer materials.
(3) CSPs with Flexible Substrate: the structure thereof is similar to the rigid substrate, but a soft substrate is used as a carrier instead; the common material is polyimide, and an elastomer is inserted between the die and the substrate in order to decrease the effect of the stress upon the devices; an arrangement—an area array—is used for rearranging the I/Os on one side of the soft carry board that opposite to the side without dies contacted thereon.
(4) Wafer-level CSPs: the external I/Os of the made devices thereof are fan-in arranged; the size of the made devices are almost the same as the size of the dies; the carrier substrate is usually a wafer; it is connected with the dies by the technique similar to that of the flip-chip, and no encapsulation process is needed, then the I/Os are rearranged as an area array on the side with dies thereon.
Besides, the flip-chip technology by die bonding or attaching chips with metal bumps onto substrate carrier, and underfilling polymer materials between the die and substrate spacing thereafter is invented to reduce the package size.
Again, as the increasing complexity of portable electronic systems, such as, mobile phone, PDA, and portable computer, etc., more functions are integrated into a single chip, thus the concept of system-on-chip (SoC) is generated. However, there are many difficulties of developing SoC, especially integrating various functions, of each are uniquely designed, having various data base, design rule, and intellectual properties (IP) from various companies, that usually takes a lot of time for integration and transformation. To have a SoC may be an ultimate goal, combining the state-of-the-art WLP and CSP technologies can make hybrid packaged ICs in rather small forms. In the other words, assembling two or more bare dies into various kinds of multichip modules (MCMs) and with final outlooks like a single packaged device, i.e., the system-in-a-package (SiP) approach. Especially the SiP approach may enable the dies to be tested in wafer-level, for example, the known good die (KGD) process. In the case of MCM and SiP, the wafer-level testing are further proceeded in order to promote the packaging yield and save the dispensable packaging cost. For the customers, by means of SiP, the cost and time for development of a system product are reduced, the performance are optimized as well.
According to the present situation of portable electronic devices, a lot of passive components are packaged into device together, these passive components or elements are like resistors, capacitors, and inductors. In order to shrink the size of packaged devices, two ways have been proposed, they are the passive devices made by low temperature co-firing ceramics (LTCC) process, and the integrated thin film passive devices (IPD). First of all, by using the conventional screen printing and sintering technology, the minimum feature size made by LTCC is around or above 50 ?m, and is hard to be controlled. It causes the made RF circuits can hardly show good high frequency performance in a repeatable and precise manner. Secondly the IPD is made normally by depositing and patterning the resistors, capacitors, and inductors materials on substrates, where these substrates are usually the wafer forms. The made RF module based on IPD will have smaller size and higher precised performance.
FIGS. 1
a
and
1
b
show an RF module in IPD (Integrated Passive Devices) format, fabricated by thin film process disclosed by Intarsia in the United States at the Systems Design Magazine on August 2000 and December 2000, respectively (see the reference materials [1], [2] and [3]).
FIG. 1
a
shows the steps of forming the electrode.
FIG. 1
b
shows the said RF module whose passive devices like inductor, capacitor, and resistor are made by the standard thin film process of IC industry. The formation of the thin film resistor, as shown in
FIG. 1
a
, a resistance layer
11
is deposited and defined on the glass substrate
10
, then a first conductive layer
12
is deposited and defined by etching or lift-off process. The first conductive layers
12
which are made onto both end of the resistance layer
11
are electrodes of resistor R. Thereafter a second isolation layer
15
is deposited and defined. Again, the formation of the integrated passive device is shown in
FIG. 1
b
; a resistant layer
11
is deposited and defined on the substrate
10
firstly, then a first metal pattern
12
is deposited and defined by etching or the lift-off method. The first metal pattern
12
is the electrodes on the both ends of the resistor R. Then, a first dielectric layer
13
and a second metal pattern
14
is deposited, thus a capacitor C is formed by the first dielectric layer
13
and two patterns—which are above and under thereof respectively—the first metal pattern
12
and the second metal pattern
14
. Afterwards, a second dielectric layer
15
is formed onto the resistor R and the capacitor C for isolation. The second dielectric layer
15
is required to be thick enough in order to cover the devices and to be applied uniformly onto the substrate. Then a lead guide hole is defined on the second dielectric layer
15
, a buffer layer (or adhesion layer)
16
is formed for advancing the interconnection and the adhesion to the follow-up conductive layer
17
Huang Yi-Mou
Lee Chengkuo
Asia Pacific Microsystems, Inc.
Dang Phuc T.
Troxell Law Office PLLC
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