Package structure and manufacturing method thereof

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

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C438S106000, C438S107000, C438S667000, C438S698000

Reexamination Certificate

active

08058102

ABSTRACT:
The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes a dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material.

REFERENCES:
patent: 2010/0301474 (2010-12-01), Yang
patent: 2011/0042798 (2011-02-01), Pagaila et al.

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