Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2009-11-10
2011-11-15
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S106000, C438S107000, C438S667000, C438S698000
Reexamination Certificate
active
08058102
ABSTRACT:
The present invention discloses a semiconductor device package structure with redistribution layer (RDL) and through silicon via (TSV) techniques. The package structure comprises an electronic element which includes a dielectric layer on a backside surface of the electronic element, a plurality of first conductive through vias across through the electronic element and the dielectric layer, and a plurality of conductive pads accompanying the first conductive through vias on an active surface of the electronic element; a filler material disposed adjacent to the electronic element; a first redistribution layer disposed over the dielectric layer and the filler material, and connected to the first conductive through vias; a first protective layer disposed over the active surface of the electronic element, the conductive pads, and the filler material; and a second protective layer disposed over the redistribution layer, the dielectric layer, and the filler material.
REFERENCES:
patent: 2010/0301474 (2010-12-01), Yang
patent: 2011/0042798 (2011-02-01), Pagaila et al.
Hu Yu-Shan
Lin Diann-Fang
Advanced Chip Engineering Technology Inc.
Kusner & Jaffe
Pham Long
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