Package structure

Details Package structure Package structure

2009-08-05

2011-11-15

Mandala, Victor A (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S686000, C257S698000, C257SE23174, C257SE23141

Reexamination Certificate

active

08058721

ABSTRACT:
Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an opposite inactive surface of the semiconductor chip respectively, the semiconductor chip having a plurality of through-silicon vias for electrically connecting the first and second electrode pads. As a result, the semiconductor chip is electrically connected to the two sides of the package structure via the through-silicon vias instead of conductive through holes, so as to enhance electrical quality and prevent the inactive surface of the semiconductor chip from occupying wiring layout space of the second surface of the core board to thereby increase wiring layout density and enhance electrical performance.

REFERENCES:
patent: 2007/0076392 (2007-04-01), Urashima et al.
patent: 2011/0018099 (2011-01-01), Muramatsu
patent: 2011/0024888 (2011-02-01), Pagaila et al.

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