Package integrated circuit having thermal enhancement and reduce

Details Package integrated circuit having thermal enhancement and reduce Package integrated circuit having thermal enhancement and reduce

1997-10-27

1999-02-23

Picardat, Kevin M.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

438121, 438125, H01L 2144

Patent

active

058743219

ABSTRACT:
According to the invention, a packaged integrated circuit includes a lid attached to a base to enclose a cavity, an integrated circuit chip or chips being attached to each of the lid and base within the cavity. Preferably, the chip or chips that generate the most heat during operation of the packaged integrated circuit are attached to the lid and the lid is made of a material having good thermal conductivity such as aluminum nitride. The chips attached to the base generate relatively little heat and so do not require a heat sink to be included in the base. The packaged integrated circuit is formed in a cavity-up configuration, thereby enabling connection pins or solder balls to be formed over the entire exterior surface of the base, increasing interconnection density. Additionally, attachment of chips to both the lid and the base allows an increased number of electronic functions to be included in one packaged integrated circuit. Further, the chip or chips attached to the lid can be tested before being committed to the base, thereby enabling defective chips to be discarded without having to discard the relatively expensive base.

REFERENCES:
patent: 4635346 (1987-01-01), Matsuzaki
patent: 5182632 (1993-01-01), Bechtel et al.
patent: 5200367 (1993-04-01), Ko
patent: 5291062 (1994-03-01), Higgins, III
patent: 5307240 (1994-04-01), McMahon
patent: 5403784 (1995-04-01), Hashemi et al.
patent: 5407864 (1995-04-01), Kim

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