Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2002-01-30
2004-10-05
Williams, Alexander Oscar (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S707000, C257S669000, C257S694000, C257S666000, C257S712000, C257S713000, C257S675000, C361S704000, C361S773000, C361S813000
Reexamination Certificate
active
06800932
ABSTRACT:
BACKGROUND OF THE INVENTION
Semiconductor devices in the form of integrated circuit chips (ICs) must typically be mounted on a flat surface such as a printed circuit board when they are incorporated into a product such as a computer or cellular phone. No surface-mount semiconductor packaging technology exists today that is capable of meeting the needs of the next-generation of discrete power semiconductor devices and ICs.
Such surface-mount power packages should include at least the following features:
1. A low electrical resistance.
2. The capability of shunting current and reducing the lateral resistance in a device's metal interconnect.
3. A low thermal resistance.
4. The capability of achieving high currents vertically (through backside) or laterally (topside).
5. High manufacturability.
6. A low intrinsic material cost.
7. A low manufacturing cost.
8. Reliable operation in power applications.
9. The ability to facilitate at least three (and preferably more) isolated connections to the semiconductor.
10. A low profile (height) and small footprint.
Power semiconductor devices and ICs come in two types, those that conduct high currents because they exhibit low on-state voltage drops (and hence low power dissipation) and those that conduct “high” currents because they dissipate large amounts of power. Because of the varied use, construction, and operation of such power devices, the first two features listed (i.e. low electrical resistance) can be achieved in lieu of the third feature (low thermal resistance), but ideally one package should offer both low electrical and thermal resistance.
The fourth feature, a high current flow laterally or vertically, specifies that a power package should ideally be applicable to both lateral and vertical power devices, but at least one of the two orientations should be high current capable.
Of course, the package must be highly manufacturable since power transistors are used in high quantities, billions of units yearly, worldwide. Any intrinsic manufacturing repeatability or yield problem would have dire consequences for the supplier and likely the user of such devices.
Another feature is low cost, including the package material cost and the cost of its manufacture. Of these, the material cost is fundamental since the prices of certain materials such as gold wire, plastic molding, copper leadframes, etc., are based on the world market for the raw material and cannot be substantially changed through simple increases in semiconductor product volume. Package designs using smaller amounts of material are inherently cheaper to produce.
The reliability of a package in a power application means it must survive operating conditions commonly encountered in power device use, such as current spikes, higher ambient temperatures than normally encountered, significant self heating, thermal shock from repeated thermal transients, etc. Repeated pulses of current or heating can provoke fatigue-related failures, particularly at metallurgical junctions and interfaces. Fewer interfaces are preferable.
Two-terminal packages are needed for diodes, transient suppressors, and fuses, while packages supporting at least three connections are useful for discrete transistors. Four connections up to eight connections are extremely valuable for a variable of smarter power semiconductor components. Beyond eight distinct connections, the use of such power package technology is concentrated on power integrated circuits.
Low profile surface mount packages, while not universally required, make it convenient for PC board manufacturing since power devices packaged in low profile packages have the same characteristics of other ICs on the same board and hence avoid the need for special handling. In some cases like battery packs, PCMCIA cards and cell phones, the low profile package may be crucial in meeting a critical thickness in the final end product.
Small footprint is generally a matter of overall product size, especially in portable electronics where size is an important consumer buying criteria—the smaller the better.
In a related consideration, the smaller the package footprint is on the board and the larger the semiconductor die it contains, the performance for a given size is greater.
While these goals may seem obvious, the fact is that today's power semiconductor-packaging technology does not meet these needs adequately, cost effectively, and in some cases, at all. Many of the disadvantages of the conventional packages are a consequence of the use of bond wires. Bond wires contribute added resistance and are ineffective in their conduction of heat, especially wires that are connected to the topside source pad in a power MOSFET, insulated gate bipolar transistor, or bipolar transistor. Several firms have attempted to develop a bond-wireless connection to the gate, but these attempts have been unsuccessful and the firms have had to revert to a wire-bonded gate connection.
One such attempt at a process flow for fabricating a power MOSFET containing a bond-wireless source connection combined with a gate bond wire is shown in FIG.
1
A. In this flow, an epoxy die attach (and partial cure) between the die and the top leadframe is then followed by flipping the die over and attaching it via epoxy to the bottom leadframe. Because of the torque applied by the tie bars to the die attach portion of the leadframe, maintaining a uniform interfacial epoxy layer is difficult at best. Moreover, in this flow, wire bonding must occur after the bond-wireless die-attach. After the wire-bond is made, molding, trimming and forming still must occur.
FIG. 1B
illustrates a top leadframe
440
epoxy-attached to die
442
. The curved-metal “camel hump” leadframe
440
(i.e. the step-up and down-set leadframe) makes a uniform die attach operation difficult. After die attach, the plan view of
FIG. 1C
illustrates the bond-wireless portion
444
of the top leadframe
440
and the shorter “diving board” piece
446
used for wire bonding the gate. Even with a tie bar tied to one side, holding leadframe
440
stable during wire bonding is difficult.
After the top leadframe
440
is attached to the die
442
, the bottom leadframe
448
is die-attached using conductive epoxy, as shown in the cross-sectional view of FIG.
1
D and the plan view of FIG.
1
E. Controlling the torque and pressure during die attach and curing is critical to a reliable product. The gate lead
446
is then wired-bonded, using a bonding wire
450
, as shown in the perspective drawing of FIG.
1
F. Mixing bonding wire and bond-wireless methods in the same package has a disadvantage in cost since the die-leadframe or die-strap assembly must be moved to a different machine to perform wire bonding. Handling the product takes time and costs money. In fact, this method has so many problems in achieving manufacturability that it may never be used commercially and may be abandoned altogether despite years of investment within the industry. Die-cracking, variable on-resistance, and on-resistance that changes during operation or burn-in are all symptomatic of this approach.
Notice that gate lead
446
is mechanically analogous to a diving board with little support of its free end during wire-bonding. Its movement makes the quality of the gate bond
452
questionable and variable.
FIG. 1G
shows another perspective drawing after plastic molding (shown as a dotted line
454
). The asymmetry of the design renders manufacturing of this approach challenging and irreproducible.
Another approach is shown in the flow diagram of FIG.
2
A. In this approach, the die is first attached to a copper strap layer to form a die and strap assembly, then subsequently the die and strap assembly is attached to a conventional leadframe. After this second attachment, the part still must be wire bonded to connect the gate of the device. Thereafter the structure is molded, trimmed and formed.
In
FIG. 2B
, again a camel hump piece of metal, in this case the “strap”
460
is aligned to the die
462
. The strap
460
has a uniform width (see
FIG. 2C
)
Choi Alex K.
Lam Allen K.
Williams Richard K.
Advanced Analogic Technologies, Inc.
Silicon Valley Patent & Group LLP
Williams Alexander Oscar
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