Package for semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame

Patent

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Details

257691, 257692, 257700, H01L 2352

Patent

active

056295596

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a novel package for mounting of semiconductor device. More particularly, the present invention relates to a package for mounting of semiconductor device, which gives reduced simultaneous switching noise to semiconductor devices and which can effectively prevent the adverse effect of the noise generating in the vicinity of the package, particularly the noise generating in the power line and the ground line, on the semiconductor device.


BACKGROUND ART

The operation of the semiconductor devices used in microprocessors, gate arrays, etc. has become increasingly fast in recent years, and the limit of the frequency allowing for the operation of microprocessor has now reached 200 MHz. This limit of the frequency allowing for said operation is anticipated to become increasingly high in the future. As the operational frequency becomes high, the semiconductor device is adversely affected more easily by the noise generating in the vicinity thereof, particularly the noise generating in the power line and the ground line.
Under the above circumstance, there was proposed a three-layer package for mounting of semiconductor device. In FIG. 1a is shown a schematic sectional view when a semiconductor device is mounted in the three-layer package. The package is constituted by a power layer 3, a ground layer 4 and a signal layer 5. The power layer and the ground layer are revered in some cases. The three layers are bonded with an adhesive tape 7. The adhesive tape 7 acts also as an insulating layer. In the three-layer package, a semiconductor device 2 is mounted; the semiconductor device is electrically connected with each layer of the package by the use of bonding wires 6; the outer leads 8 of the signal layer are used as leads for electrical connection with the outside. That is, the electrical connection of the power layer 3 and the ground layer 4 with the outside is conducted by their connection with one or more of the fine outer leads 8 of the signal layer. The semiconductor device and the package, including the above connected portions and a part of the outer leads 8, are sealed with a resin 9.
In such a three-layer package, the power layer and the ground layer have many throughholes formed therein.
In FIG. 1b is shown a schematic plane view of a typical example of the power layer or the ground layer. In FIG. 1b, the power layer or the ground layer has a square shape and has outer leads around the outside. There is an electro-conductive portion between the outer leads and the Inner lead formed in the shape of a frame In the center of the power layer or the ground layer, and many throughholes are formed in the electro-conductive portion.
The adhesive tape 7 acting also as an insulating layer adheres to the sealing resin through the above throughholes, and further the adhesive tape 7 present in the form of two layers adhere to each other through the throughholes, whereby a three-layer structure is formed. This state is appreciated by referring to FIG. 1c which is a schematic sectional view of the package.
That is, in FIG. 1c, the adhesive tape 7a and the adhesive tape 7b are bonded through the throughholes and act so as to laminate the signal layer 5, the power layer 3 and the ground layer 4 more solidly.
In such a three-layer package, the self-inductances of the power layer and the ground layer are relatively low and the power line and ground line noise is relatively low.
It is, however, desired to develop a package for mounting of semiconductor device, in which the power line and ground line noise is lower.


DISCLOSURE OF THE INVENTION

The present inventor made a research in order to develop a package in which the power line and ground line noise is lower. As a result, the present inventor found out the following facts and completed the present invention.
(1) In the conventional three-layer package, the throughholes formed in the power layer and the ground layer act so as to increase the self-inductances of these layers. By eliminating the throughholes, the power lin

REFERENCES:
patent: 5196725 (1993-03-01), Mita et al.
patent: 5220195 (1993-06-01), McShane et al.
patent: 5399804 (1995-03-01), Yoneda et al.

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