Package for packing semiconductor devices and process for produc

Details Package for packing semiconductor devices and process for produc Package for packing semiconductor devices and process for produc

1987-05-11

1989-05-16

Grimley, Arthur T.

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

437221, H01L 2310

Patent

active

048312126

ABSTRACT:
In a package comprising a chip mounting base and a cap to be fitted on the base, the base comprises a metal substrate, an electrically insulating ceramic layer formed on the metal substrate, a patterned metal layer formed on the ceramic layer in a selected area thereof, a first mixed layer formed in an area near the interface between the metal substrate and the ceramic layer, and a second mixed layer formed in an area near the interface between the ceramic layer and the metal layer, and the cap comprises a metal substrate, an electrically insulating ceramic layer formed in at least the marginal portion of the side of the metal substrate which faces the base, and a mixed layer that is formed in an area near the interface between the metal substrate and the cermaic layer.

REFERENCES:
patent: 4577056 (1986-03-01), Butt
patent: 4656499 (1977-04-01), Butt

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