Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2002-05-28
2004-10-26
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S712000, C257S777000, C257S787000
Reexamination Certificate
active
06809416
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a package for an integrated circuit. In particular, the present invention relates to techniques for achieving a low thermal resistance package for an integrated circuit.
DISCUSSION OF THE RELATED ARTS
The temperature of a PN junction in a semiconductor device is an important parameter that affects the proper operation of the semiconductor device. Thus, the package for an integrated circuit is designed with much emphasis on its ability to dissipate the heat generated during device operation. The thermal performance of a package is typically characterized by several figures of merit: &thgr;
JA
, &psgr;
JT
, and &thgr;
JC
. &thgr;
JA
is given by:
&thgr;
JA
=(
T
J
−T
A
)/
P
H
where T
J
and T
A
are respectively the junction and ambient air temperatures, and P
H
is the power dissipation of the device. Similarly, &psgr;
JT
and &thgr;
JC
are given by:
&psgr;
JT
=(
T
J
−T
T
)/
P
H
&thgr;
JC
=(
T
J
−T
C
)/
P
H
where T
T
and T
C
are respectively the temperature at the top-center of the package, and the temperature of the case. &psgr;
JT
is typically used to estimate junction temperature from a measurement of T
T
. &thgr;
JC
is an important parameter in designing a package to be operated with a heat sink attached to its top surface.
In designing integrated circuits, often times an accurate estimate of the power dissipation of an integrated circuit is not available until after the integrated circuit design is substantially complete, or after the integrated circuit is first fabricated. However, at that stage, if one discovers that the intended package for the integrated circuit would not handle that power dissipation, the corrective options available are limited and expensive. For example, one may consider using a more expensive ceramic package, attach an external heat sink or fan, or redesign the integrated circuit to a lower current density. A redesign of the integrated circuit (e.g., by increasing the die size) is expensive not only because of the additional engineering and manufacturing tooling costs, there are also costs associated with the higher manufacture cost per die and time delay to market.
In one embodiment described below, the present invention provides enhanced heat dissipation performance in an integrated circuit package having multiple semiconductor dies. Integrated circuits having multiple semiconductor dies in one package are known in the prior art. For example,
FIG. 1
shows prior art multi-chip module
100
having semiconductor die
104
bonded conventionally (e.g., using thermally conductive adhesive) to semiconductor die
102
, which in turn is bonded to insulating substrate
101
. Semiconductor die
104
may be, for example, a static random access memory (SRAM) integrated circuit and semiconductor die
102
may be, for example, a “flash” electrically programmable read-only memory (“flash EPROM”). Substrate
101
may be, for example, a printed circuit board coupled by electrical conductors (not shown) on the printed circuit board to external leads of multi-chip module
100
. In
FIG. 1
, bond wires
105
a
and
105
b
couple bonding pads of the electronic circuit in semiconductor die
102
to electrical conductors on the printed circuit board. Similarly, bond wires
103
a
and
103
b
couple bonding pads of the electronic circuit in semiconductor die
104
to electrical conductors on the printed circuit board.
SUMMARY OF THE INVENTION
A method for enhancing thermal performance of an integrated circuit package attaches a dummy die to the semiconductor die of the integrated circuit. The dummy die is then thermally coupled through external terminals to the conductive layers of a printed circuit board. In one embodiment, the integrated circuit package includes an insulating substrate on which the dummy die is attached. Conductive vias thermally connect conductive terminals provided on one side of the insulating substrate to conductive terminals provided on the other side of the insulating substrate. In one embodiment, the integrated circuit package is provided as a ball grid array (BGA) package. In addition, multiple layers of conductors can be provided in both the insulating substrate of the integrated circuit and in the external printed circuit board.
Because one can increase the size of the dummy die without redesign to increase the surface area from which heat can dissipate, and to allow the number of thermal vias that can be in thermal contact with the dummy die, a power dissipation problem discovered at a late stage of integrated design can be thus corrected very inexpensively.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.
REFERENCES:
patent: 5815372 (1998-09-01), Gallas
patent: 6191477 (2001-02-01), Hashemi
patent: 6218731 (2001-04-01), Huang et al.
patent: 6265771 (2001-07-01), Ference et al.
patent: 6353263 (2002-03-01), Dotta et al.
patent: 6462274 (2002-10-01), Shim et al.
patent: 6545366 (2003-04-01), Michii et al.
patent: 6621169 (2003-09-01), Kikuma et al.
patent: 2002/0185744 (2002-12-01), Katagiri et al.
patent: 2003/0230799 (2003-12-01), Yee et al.
Intersil Corporation
Kwok Edward C.
MacPherson Kwok & Chen & Heid LLP
LandOfFree
Package for integrated circuit with thermal vias and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Package for integrated circuit with thermal vias and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Package for integrated circuit with thermal vias and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3272382