Package for enclosing semiconductor elements

Details Package for enclosing semiconductor elements Package for enclosing semiconductor elements

1982-07-20

1984-07-03

Goldberg, E. A.

Electricity: electrical systems and devices

Discharging or preventing accumulation of electric charge

357 84, 174 52FP, 206328, 361220, H05K 706

Patent

active

044582919

ABSTRACT:
A package for enclosing semiconductor elements having side surfaces at which cross sections of conductive wires for receiving a voltage to effect electric plating are exposed. The side surfaces are provided with a static electricity-preventing device, such recesses formed in the side surfaces, insulating films formed on the side surfaces or removable frames positioned on the side surfaces, so that a high voltage due to static electricity from an exterior source is not applied to the conductive wires.

REFERENCES:
patent: 3345541 (1967-10-01), Cobaugh et al.
patent: 4084210 (1978-04-01), Forrest
patent: 4327832 (1982-05-01), de Matteo

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