Package for an integrated circuit structure

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package

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Details

257698, 257701, 257704, H01L 2348, H05K 706

Patent

active

052237419

ABSTRACT:
A package for housing a large scale semiconductor integrated circuit structure, such as a wafer or an assemblage of chips in a hybrid configuration, comprises a heat spreading and dissipating base plate to which the wafer or hybrid circuit is directly bonded. Electrical connections from the periphery of the package interior to the wafer are preferably made with equal length TAB (Tape Automated Bonding) strips connected to electrically conductive pads located along a diameter of the wafer or the centerline of the hybrid circuit. If hermeticity is desired, the integrated circuit structure is encircled by a boundary strip of sandwich construction through which signals are routed, and to which a lid is attached. For hermeticity, the integrated circuit structure is surrounded on all sides with a barrier combining metal and ceramic; the remainder of the package may be constructed from conventional printed circuit board materials. The package can be made arbitrarily large without encountering the problems typically associated with hermetic structures which utilize large areas of ceramic materials.

REFERENCES:
patent: 3554821 (1971-01-01), Caulton et al.
patent: 3908155 (1975-09-01), Skinner
patent: 3959579 (1976-05-01), Johnson
patent: 4000509 (1976-12-01), Jarvela
patent: 4076955 (1978-02-01), Gates et al.
patent: 4151548 (1979-04-01), Klein et al.
patent: 4172261 (1979-10-01), Tsuzuki et al.
patent: 4203127 (1980-05-01), Tegge, Jr.
patent: 4441119 (1984-04-01), Link
patent: 4498121 (1985-02-01), Breedis et al.
patent: 4577214 (1986-03-01), Schaper
patent: 4603374 (1986-07-01), Wasielewski
patent: 4614194 (1986-09-01), Jones et al.
patent: 4672151 (1987-06-01), Yamamura et al.
patent: 4680618 (1987-07-01), Kuroda et al.
patent: 4745455 (1988-05-01), Glascock, II et al.
patent: 4755910 (1988-07-01), Val
patent: 4811166 (1989-03-01), Alvarez et al.
patent: 4825282 (1989-04-01), Fukaya
patent: 4873566 (1989-10-01), Hokanson et al.
patent: 4879588 (1989-11-01), Ohtsuka et al.
patent: 4899208 (1990-02-01), Dietsch et al.
patent: 4961788 (1988-08-01), Dietrich et al.
patent: 4982311 (1991-01-01), Dehaine et al.
"Film on Metal Leaded Chip Carrier", IBM TDB, vol. 31, No. 1, Jun./1988, p. 2.
"Common Substrate Design for Wirebond/Hermetic VLSI Devices", IBM TDB, vol. 27, No. 11, Apr./85, p. 6366.
Costlow, TI, Hitachi develop package for 16-Mbit, Electronic Engineering Times, Issue 628, Feb. 11, 1991, (p. 1 and p. 110).
Wafer Scale Integration, G. Saucier and J. Trilbe (Editors), Elsivier Science Publishers B.V. 1986, pp. 321-344, "Wafer Scale Integration (WSI) Packaging" by Christian Val.
International Workshop on Defect and Fault Tolerance in VLSI Systems, Sprigfield, Mass. (IEEE), Oct. 6, 1988, "Wafer Scale Revisited," by Douglas L. Peltzer, Tactical Fabs, Inc.

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