Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-12-21
2001-10-30
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S127000
Reexamination Certificate
active
06309908
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method of making and a package for an electronic component, particularly an integrated circuit, which effectively eliminates die cracking in the package and improves reliability of the package.
BACKGROUND OF TH INVENTION
The demand for electronic component packages, especially packages for flip-chip integrated circuits, that are both reduced in size and more reliable has increased dramatically. Additionally, the demand for certain semiconductor devices, of increasing size has also grown. These factors, coupled with the inherent issues of combining device substrate and package materials having different Coefficients of Thermal Expansion (CTE), result in failure of the packages. Most package failures are due to failure of the joints of the package, particularly solder joints, and cracking in the semiconductor devices or dies.
The major types of die cracking are vertical cracking initiated from the die backside and horizontal cracking initiated from the die edge. Vertical cracks begin on the backside of the die and travel downward from the top of the chip to the substrate and are frequently caused by backside defects of the die. Horizontal cracks are those cracks that occur along the edges of the die and are most frequently due to die singulation.
One means for eliminating die stress in an electronic assembly is described in Sylvester et al. (U.S. Pat. No. 5,868,887). In the prior art method one surface of a die is connected to a package and an opposite die surface is disposed over a constraining ring that is mounted to the package. The lid has a size, shape and CTE selected to generate a bending moment that opposes bending moments resulting from connecting the die to the package.
The requirement of a stiffener ring in the patented method results in a package that is more costly and is less robust. Additionally, the selection of materials that have matching CTE values limits the flexibility of the package design and ease of manufacturing.
McCormick et al. (U.S. Pat. No. 5,909,057) describes a semiconductor package that includes a heat spreader/stiffener that is equipped with a plurality of apertures to provide access for underfill to flow in the space between the die and the substrate. A conventional adhesive is used to attach the stiffener component to the die. The resulting package is, however, rigid and prone to die cracking. Further, moisture may be trapped in the package during the patented manufacturing process that damages the electronic components.
A method and device to encapsulate integrated circuits is claimed in wang et al: (U.S. Pat. No. 5,817,545). A special mold surrounds the chip to be encapsulated in a cavity and the encapsulant is injected into the cavity at an elevated pressure and/or temperature. Additional equipment and process steps are required to perform the high pressure and temperature encapsulation.
Accordingly, a need exists for an improved package for an electronic component that effectively eliminates both horizontal and vertical cracking in the semiconductor device of the package to provide a more reliable package that is easier to manufacture.
A further need exists to improve the reliability of the joint connections, particularly solder joints to provide a more robust semiconductor package.
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Mercado Lei L.
Sarihan Vijay
Huffman A. Kate
Jones Josetta I.
Motorola Inc.
Niebling John F.
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