Package for a semiconductor device and a semiconductor device

Details Package for a semiconductor device and a semiconductor device Package for a semiconductor device and a semiconductor device

1997-05-30

2000-02-22

Dutton, Brian

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

257700, 257706, 257778, 257 48, 257713, 257712, 257686, H01L 23495, H05K 720

Patent

active

060283580

ABSTRACT:
A semiconductor package and semiconductor device are provided which enable manufacturing of same with ease of inspection, good reliability, and good thermal characteristics. An insulator made of an organic material and a wiring pattern formed by a metallic foil are formed on top of a metallic base substrate, thereby forming a laminated structure. The metallic base substrate has a plurality of electrically insulated continuity checking terminals. The metallic base substrate, the continuity checking terminals, and the wiring pattern are connected by via holes which pass through the insulator at prescribed locations. The insulator and wiring pattern is removed at a prescribed location at which a semiconductor chip is to be mounted. The exposed metallic base substrate is formed as a cavity of a prescribed depth.

REFERENCES:
patent: 4829403 (1989-05-01), Harding
patent: 5668405 (1997-09-01), Yamashita
patent: 5763939 (1998-06-01), Yamashita
Electronic News, Mar. 6, 1995.
Nikkei Microdevices, pp. 61 to 65, Jun. 1995.
Electronic Materials, pp. 59 to 63, Oct. 1996.
Electronic News, Jan. 22, 1996.
Electronic Components and Technology Conference, pp. 707 to 712, 1996.
Electronic Components and Technology Conference, pp. 1217 to 1221, 1996.
Electronic Components and Technology Conference, pp. 1271 to 1277, 1996.

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