Package for a semiconductor device

Details Package for a semiconductor device Package for a semiconductor device

2008-03-18

2008-03-18

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C257SE21499

Reexamination Certificate

active

07344916

ABSTRACT:
A semiconductor device39.The device includes an interposer31having two major surfaces. The first surface311includes patterned metal conductors and bond pads351,and the second surface includes an array of solder balls33.The device includes a semiconductor chip30having a top surface and a back surface, the back surface of the chip adjacent the interposer31,and the top surface including a plurality of terminals. Also included is a layer of polymeric material34disposed on the first surface311of the interposer covering the area of the interposer over the solder ball array. At least a portion of the polymeric layer is between the chip30and the interposer31.The device further includes a plurality of electrical connections35between the chip terminals and the bond pads351on the interposer.

REFERENCES:
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patent: 6020219 (2000-02-01), Dudderar et al.
patent: 6127724 (2000-10-01), DiStefano
patent: 6232661 (2001-05-01), Amagai et al.
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patent: 6265782 (2001-07-01), Yamamoto et al.
patent: 6720209 (2004-04-01), Igarashi et al.
patent: 2002/0070462 (2002-06-01), Fujisawa et al.
patent: 2003/0134450 (2003-07-01), Lee

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