Package configuration and manufacturing method enabling the...

Semiconductor device manufacturing: process – Voltage variable capacitance device manufacture

Reexamination Certificate

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C361S780000, C257S700000

Reexamination Certificate

active

07829424

ABSTRACT:
The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

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A. Feingold et al., “Compliant Dielectric and Magnetic Materials for Buried Components”, IMAPS 2002, Denver, URL: http://www.electroscience.com/publications/IMAPS2002(2).pdf, 6 pages.

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