Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-05-12
2003-12-02
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S698000
Reexamination Certificate
active
06657292
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor mounting technology, and more specifically to a structure of a package of a semiconductor device for mounting semiconductor elements.
2. Background Art
FIG. 5
is a pattern diagram illustrating the state where a multiple pin package is mounted on a mounting board in a semiconductor device according to the conventional art.
FIG. 5
shows an arrangement of major portions of a multiple pin package mounted on a top surface of a mounting board and viewed from the bottom side of the mounting board.
In
FIG. 5
, reference numeral
1
shows a mounting board on which a plurality of ball-grid array packages are to be mounted, and the mounting board
1
extends beyond the periphery of the shown area in the drawing. Reference numeral
2
shows a multiple pin BGA package (hereafter simply referred to BGA) mounted on a determined portion of the mounting board
1
; reference numeral
3
shows foot prints (pads) of the mounting board
1
; reference numeral
4
shows a region of the mounting board
1
inside the broken line where wiring, to be connected to the multiple pin BGA
2
, is densely disposed; reference numeral
5
shows some electronic elements mounted on the mounting board
1
; and reference numeral
6
shows bypassing wiring in the mounting board
1
connecting the two electronic elements
5
with each other.
In a conventional multiple pin BGA
2
, as shown in
FIG. 5
, the footprints
3
of the multiple pin BGA
2
are arranged in a lattice pattern, and signal lines are connected between chips and the mounting board
1
. In such a conventional multiple pin BGA
2
, a region
4
of high wiring density is formed because of a number of connections to the multiple pin BGA
2
, and it is not easy to draw signal lines from the multiple pin BGA
2
. Accordingly, the number of layers in the mounting board
1
need to be increased, or the lead lines of signals are forced to bypass in the vicinity of the region
4
. An example of such a bypassed wiring is the bypassed wiring
6
for connecting the two electric elements
5
each other as shown in FIG.
5
.
As described above, in mounting a conventional multiple pin BGA
2
on a mounting board
1
, it is difficult to draw signal lines in the mounting board
1
from the multiple pin BGA
2
. Therefore, the number of layers in a mounting board
1
is to be increased. The signal lines have to be bypassed in the vicinity of the region
4
.
The object of the present invention is to solve the above problem, and to provide a package board for a multiple-pin ball grid array package, which reduces the wiring density in the mounting board at a mounting region of a multiple-pin BGA, without increasing the number of layers in the mounting board. The further objects of the present invention is to provide a multiple-pin ball grid array package formed on such a package board.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a package board for a multiple-pin ball grid array package comprises a base board. A plurality of first external terminals are arranged on one major surface of the base board. A plurality of first internal wiring is provided in the base board for connecting the first external terminals to an electronic element to be mounted on the other major surface of the base board. A plurality of second external terminals are arranged on the one major surface of the base board. Further, at least one second internal wiring is provided for directly connecting at least two of the second external terminals each other.
According to another aspect of the present invention, a multiple-pin ball grid array package comprises a package board and at least an electronic element mounted on the package board. Further, the package board includes a base board. A plurality of first external terminals are arranged on one major surface of the base board. A plurality of first internal wiring is provided in the base board for connecting the first external terminals to an electronic element mounted on the other major surface of the base board. A plurality of second external terminals are arranged on the one major surface of the base board. Further, at least one second internal wiring is provided for directly connecting at least two of the second external terminals each other.
According to another aspect of the present invention, a semiconductor device comprises a mounting board, a multiple-pin ball grid array package mounted on the mounting board, and a plurality of other electronic elements mounted on the mounting board. Further, the multiple-pin ball grid array package includes a package board and at least an electronic element mounted on the package board. Still further, the package board has at least one pair of external terminals and an internal wiring directly connecting the pair of external terminals each other. In addition, at least two of the electronic elements are electrically connected each other through the second external terminals and the second internal wiring of the package board of the multiple-pin ball grid array package.
According to another aspect of the present invention, a semiconductor device comprises a mounting board, a multiple-pin ball grid array package mounted on one major surface of the mounting board and a package board for a multiple-pin ball grid array package mounted on other major surface of the mounting board. The package board for a multiple-pin ball grid array package includes at least one pair of external terminals and an internal wiring directly connecting the pair of external terminals each other. Further, one of the pair of external terminals of the package board for a multiple-pin ball grid array package is electrically connected to the multiple-pin ball grid array package through the mounting board.
Other and further objects, features and advantages of the invention will appear more fully from the following description.
REFERENCES:
patent: 4221047 (1980-09-01), Narken et al.
patent: 5714801 (1998-02-01), Yano et al.
patent: 6057600 (2000-05-01), Kitazawa et al.
patent: 6104088 (2000-08-01), Hatano et al.
patent: 0 475 269 (1992-03-01), None
patent: 62-261191 (1987-11-01), None
Cao Phat X.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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