P-type flip-flop

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

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327199, 327225, H03K 3356

Patent

active

056380186

ABSTRACT:
A P-type flip-flop, which selectively functions in a D-type flip-flop mode or latch mode depending on its clock signal input. The P-type flip-flop has an output changing states to follow its data input at a leading edge of its clock input, the output then does not change states for a period .epsilon., and then the output changing states to match its data input after the period .epsilon. if a signal is received at its clock input having a period greater than .epsilon.. With a pulse applied at the clock input having a width less than .epsilon., the P-type flip-flop is edge sensitive functioning similar to a D-type flip-flop. With a pulse with longer than .epsilon. applied to the clock input, the P-type flip-flop appears transparent similar to a latch.

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patent: 5032741 (1991-07-01), Smith
patent: 5189315 (1993-02-01), Akata
"Circuit Scheme to improve chip data hold time", Technical Disclosure Bulletin, Dec. 1990, vol. 33, No. 7, pp. 185-189.
IBM Technical Disclosure Bulletin, vol. 30, No. 4, Sep. 1987, Armonk, NY, USA (pp. 1448-1450).

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