P.sup.+ Buried layer for I.sup.2 L isolation by ion implantation

Details P.sup.+ Buried layer for I.sup.2 L isolation by ion implantation P.sup.+ Buried layer for I.sup.2 L isolation by ion implantation

1977-04-28

1979-03-13

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148187, 357 47, 357 91, 357 92, H01L 2704, H01L 21265, H01L 2122, H01L 2972

Patent

active

041440986

ABSTRACT:
A selected transistor in an integrated circuit formed in an N-type substrate is isolated from the substrate and from other transistors formed therein by surrounding an N-type island within the substrate with a P-type shell and forming the selected transistor in and above the N-type island.

REFERENCES:
patent: 3768150 (1973-10-01), Sloan, Jr. et al.
patent: 3865648 (1975-02-01), Castrucci et al.
patent: 3999215 (1976-12-01), Aagaard
patent: 4005470 (1977-01-01), Tucci et al.
patent: 4038680 (1977-07-01), Yagi et al.
patent: 4043849 (1977-08-01), Kraft et al.
patent: 4045251 (1977-08-01), Graul et al.
patent: 4047975 (1977-09-01), Widmann
patent: 4076556 (1978-02-01), Agraz-Guerena et al.
Berger et al., "Base Ring Transistor--," IBM-TDB, 14 (1971), 302.

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