P+ Silicon integrated circuit interconnection lines

Details P+ Silicon integrated circuit interconnection lines P+ Silicon integrated circuit interconnection lines

1976-04-30

1977-11-08

Wojciechowicz, Edward J.

357 4, 357 23, 357 54, 357 59, 357 68, H01L 2712, H01L 2978, H01L 2934, H01L 2906

Patent

active

040578240

ABSTRACT:
An improved interconnecting line for an integrated circuit comprising a P+ silicon island having an optional first layer of silicon dioxide or a like material thereon and a second layer of silicon nitride or a like material adjacent the first layer, is provided. The line may be manufactured by improvements in the standard P channel MOS or MNOS processing method wherein the line is formed concomitantly with the island upon definition of the silicon. The line may be subsequently coated with silicon dioxide during formation of a gate oxide for a MNOS device and then coated with silicon nitride.

REFERENCES:
patent: 3749610 (1973-07-01), Swann et al.
patent: 3764413 (1973-10-01), Kakizaki et al.

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