P/N junction device having porous emitter

Details P/N junction device having porous emitter P/N junction device having porous emitter

1993-03-29

1994-11-01

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

With specified impurity concentration gradient

With high resistivity

257130, H01L 2912

Patent

active

053609905

ABSTRACT:
In a semiconductor P/N junction device, a porous emitter is provided which has high saturation current to limit injected charge when the device is conducting. The porous emitter includes a lightly doped region abutting a contact on the surface of the device to regulate minority carrier injection under forward bias and shield the contact from stand-off field when the device is not conducting. One or more heavily doped regions are provided in the first region to provide low contact resistance for the flow of majority carriers into the emitter.

REFERENCES:
patent: 4587547 (1986-05-01), Amemiya et al.
patent: 5063428 (1991-11-01), Schlangenotto
Arnould, "Dispositifs De Puissance Dipolaires Rapid A Porteurs De Duree De Vie Tres Elevee," Journees Electronique De Puissance De Futur, Bordeaux, Jun. 1-3, 1988.
Schlangenotto, "Improved Recovery of Fast Power Diodes with Self-Adjusting p Emitter Efficiency," IEEE Electron Device Letters, vol. 10, No. 7, Jul. 1989, pp. 322-324.
Shimizu, "High-Speed Low-Loss p-n Diode Having a Channel Structure," IEEE Transactions on Electron Devices, vol. ED-31, No. 9, Sep. 1984, pp. 1314-1319.
Mehrotra, "Comparison of High Voltage Power Rectifier Structures," 5th International Symposium on Power Semiconductor Devices and IC's, 0-7803-1313-5/93/0000-0199/$3.00.COPYRGT. 1993 IEEE, pp. 199-204.

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