P-channel negative pumps

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Reexamination Certificate

active

06621326

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to integrated circuits and, in particular, to pump circuits used in integrated circuits.
2. Description of the Related Art
In some integrated circuits, it is desirable to have a circuit that provides a high negative voltage. This is particularly true for integrated circuits that include memory devices, such as, for example, electrically erasable programmable read-only-memory (EEPROM) devices. The high negative voltage is applied to control gates of memory cells during erasure to erase the data stored in the memory cells.
An example of a pump circuit that provides a negative voltage is described in U.S. Pat. No. 5,406,517. Some P-channel negative charge pumps, such as that of U.S. Pat. No. 5,406,517, operate with a power supply voltage V
CC
of 5 volts. However, at lower power supply voltages, such as 3 volts or lower, these charge pumps are made impractical due to source bias and large body-effect coefficients, unless clock signals themselves are pumped to a higher voltage than the power supply voltage V
CC
.
As a result, there has been a need for a charge pump circuit that is practical at lower power supply voltages.
SUMMARY OF THE INVENTION
The present invention encompasses a charge pump circuit. In one embodiment, the charge pump circuit of the present invention includes: a first pumping stage including a first switch and a second switch coupled to the first switch; and at least a second pumping stage coupled to the first pumping stage, where the second pumping stage includes a third switch and a fourth switch coupled to the third switch; where the first and second switches are in opposite states, further where immediately prior to the first switch transitioning from an off state to an on state, the second switch and the fourth switch are on.
In one embodiment, the third and fourth switches are in opposite states, and immediately prior to the third switch transitioning from an off state to an on state, the second switch and the fourth switch are on.


REFERENCES:
patent: 5406517 (1995-04-01), Chang et al.
patent: 5973979 (1999-10-01), Chang et al.
patent: 6097161 (2000-08-01), Takano et al.
patent: 6130572 (2000-10-01), Ghilardelli et al.
patent: 6137344 (2000-10-01), Miki
patent: 6157242 (2000-12-01), Fukui
patent: 6198342 (2001-03-01), Kawai
patent: 6459328 (2002-10-01), Sato

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