P-channel NAND flash memory and operating method thereof

Details P-channel NAND flash memory and operating method thereof P-channel NAND flash memory and operating method thereof

2006-06-13

2006-06-13

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185330

Reexamination Certificate

active

07061805

ABSTRACT:
A p-channel NAND flash memory includes a plurality of memory cells in series connection between a p-type source region and a p-type drain region. Each memory cell includes a tunneling dielectric layer, a floating gate, and a control gate. An erase gate is formed between two adjacent memory cells, and a p-type doped region is formed in the substrate between two adjacent memory cells. A select transistor is formed between the p-type drain and the cell nearest to the p-type drain. The cells in the p-channel NAND flash memory is programmed by band-to-band tunneling induced hot carrier injection, and erased via F-N tunneling.

REFERENCES:
patent: 2004/0057286 (2004-03-01), Chen et al.
patent: 2005/0087794 (2005-04-01), Chen et al.
Article titled “Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a P-channel Cell” jointly published by Ohnakado et al. in 1995. (4 pages).

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