Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2006-07-11
2009-12-15
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257SE29312
Reexamination Certificate
active
07633101
ABSTRACT:
A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, gate and drain opening sizes, said dielectric layer having a nitride top layer. Metal is deposited on top of said dielectric layer to fill said openings and the metal is polished back to the top of the dielectric layer to achieve thin source, drain and gate contacts. Some embodiments include an anti-leakage poly-silicon layer lining the contact holes and all embodiments where spiking may occur include a barrier metal layer.
REFERENCES:
patent: 5618688 (1997-04-01), Reuss et al.
patent: 6303961 (2001-10-01), Shibib
patent: 6649462 (2003-11-01), Azuma et al.
patent: 6774417 (2004-08-01), Lin et al.
patent: 6979863 (2005-12-01), Ryu
patent: 2003/0090604 (2003-05-01), Song et al.
patent: 2004/0053465 (2004-03-01), Hong
patent: 2005/0151171 (2005-07-01), Hao et al.
patent: 2006/0008958 (2006-01-01), Yeo et al.
patent: 2007/0128787 (2007-06-01), Higashitani
Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authorityfor International Application No. PCT/US07/73134; 12 pages, Feb. 19, 2008.
Adib R. Hamadé and José F. Albarrán;A JFET/Bipolar Eight-Channel Analog Multiplexer; IEEE Journal of Solid-State Circuits; vol. SC-10, No. 6; pp. 399-406, Dec. 1975.
Hiromitsu Takagi and Gota Kano;Complementary JFET Negative-Resistance Devices; IEEE Journal of Solid-State Circuits; vol. SC-10, No. 6; pp. 509-515, Dec. 1975.
Kurt Lehovec and Rainer Zuleeg;Analysis of GaAs FET's for Integrated Logic; IEEE Transactions on Electron Devices; vol. Ed-27, No. 6; pp. 1074-1091, Jun. 1980.
Osamu Ozawa;Electrical Properties of a Triode-Like Silicon Vertical-Channel JFET; IEEE Transactions on Electron Devices; vol. ED-27, No. 11; pp. 2115-2123, Nov. 1980.
R. Zuleeg;Complementary GaAs Logic; McDonnell Douglas Astronautics Company; 70 pages, Aug. 04, 1982.
Lis K. Nanver and Egbert J. G. Goudena;Design Considerations for Integrated High-Frequency p-Channel JFET's; IEEE Transactions on Electron Devices; vol. 35, No. 11; pp. 1924-1934, Nov. 1988.
Patent Pending U.S. Appl. No. 11/261,873 entitledIntegrated Circuit Using Complementary Junction Field Effect Transistor and MOS Transistor in Silicon and Silicon Alloysin the name of Ashok K. Kapoor; 93 total pages, filed Oct. 28, 2005.
Patent Pending U.S. Appl. No. 12/276,574 entitledOxide Isolated Metal Silicon-Gate JFETin the name of Madhukar B. Vora, et al.; 45 total pages, filed Nov. 24, 2008.
Kapoor Ashok Kumar
Vora Madhukar B.
Baker & Botts L.L.P.
Budd Paul A
DSM Solutions, Inc.
Jackson, Jr. Jerome
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