Oxide isolated integrated injection logic with selective guard r

Details Oxide isolated integrated injection logic with selective guard r Oxide isolated integrated injection logic with selective guard r

1974-10-29

1976-06-08

Larkins, William D.

Metal treatment

Stock

Ferrous

148175, 357 35, 357 36, 357 46, 357 50, 357 52, 357 89, H01L 2704, H01L 2972

Patent

active

039627179

ABSTRACT:
A process for fabricating oxide-isolated vertical bipolar transistors and complementary oxide-isolated lateral bipolar transistors incorporates the steps of growing a doped epitaxial layer of single-crystal silicon on a silicon substrate, applying a first insulation material in a selected pattern over the epitaxial layer to define oxide-isolation regions and device regions, etching grooves in the areas in which oxide-isolation regions will be formed, applying a self-aligned base insulation material over those portions of the interface between the first insulation material and the grooves which bound the region between the base of any vertical bipolar transistor to be formed and the emitter of any lateral bipolar transistor to be formed, applying an impurity of a conductivity type opposite to the conductivity type of the epitaxial layer to those groove areas not covered by the self-aligned base insulation material, the impurity serving to prevent emitter-to-collector inversion along the wall of the base of any vertical bipolar transistor without shorting the emitter and collector of any lateral bipolar transistor, forming oxide-isolation regions in the grooves and forming the vertical bipolar transistors and the lateral bipolar transistors in the device regions. The process of the present invention will produce discrete lateral bipolar transistors, discrete vertical bipolar transistors capable of operation in the conventional mode or in the inverse mode, or a composite structure which merges both a vertical bipolar transistor and a lateral bipolar transistor together on the same silicon island to form an injection-logic gate in which the base of the vertical bipolar transistor serves as the collector of the lateral bipolar transistor, the vertical transistor being operated in the inverse mode.

REFERENCES:
patent: 3386865 (1968-06-01), Doo
patent: 3500143 (1970-03-01), Lamming
patent: 3648125 (1972-03-01), Peltzer
patent: 3736477 (1973-05-01), Berger et al.
patent: 3783047 (1974-01-01), Paffen et al.
patent: 3873383 (1975-03-01), Kooi
patent: 3873989 (1975-03-01), Schinella et al.
Berger, "The Injection Model...(MTL)," IEEE Journal of Solid-State Circuits, vol. SC-9, No. 5, Oct. 1974, pp. 218-224.
Evans et al., "Oxide-Isolated Monolithic Technology...", IEEE Journal of Solid-State Circuits, vol. SC-8, No. 5, Oct. 1973, pp. 373-379.
Wiedmann, "Injection-Coupled Memory", IEEE Journal of Solid-State Circuits, vol. SC-8, No. 5, Oct. 1973, p. 337.

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