Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-04-28
2001-03-13
Riley, Shawn (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S280000, C323S281000, C361S018000, C361S091200
Reexamination Certificate
active
06201375
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to low drop out (LDO) voltage regulators, and more particularly to improvements therein which make voltage regulator respond better than prior LDO voltage regulators to output overvoltages caused by rapid load current transients.
FIG. 1
illustrates a low drop out voltage regulator which is believed to be representative of the closest prior art, described in detail in U.S. Pat. No. 5,864,227, by Borden et al. The voltage regulator shown in prior art
FIG. 1
includes a P-channel output transistor MPX having its source connected to an unregulated voltage input Vcc and its drain connected to a regulated output voltage V
OUT
. (The “output” transistors referred to herein also are commonly referred to as “pass” transistors.) Its gate is connected to an error amplifier A
1
having its (−) input connected to V
REF
and its (+) input connected to a feedback voltage V
FB
produced by a voltage divider R
1
,R
2
. A discharge circuit PD
1
includes a P-channel discharge transistor MPD having its source connected to V
OUT
and its drain connected to ground. The discharge circuit PD
1
includes a comparator C
1
having an output connected to the gate of discharge transistor MPD. The (−) input of comparator C
1
is connected to the output of error amplifier A
1
, and the (+) input of comparator C
1
is connected to a reference voltage V
TRIP
, which is offset from ground by a suitable amount.
Comparator C
1
compares the voltage applied by error amplifier A
1
to the gate of output transistor MPX to V
TRIP
to determine whether or not error amplifier A
1
is “in control” of its output, or whether error amplifier A
1
has “saturated” in attempting to turn output transistor MPX off. If the output of error amplifier A
1
exceeds V
TRIP
, the LDO voltage regulator “assumes” that a V
OUT
overvoltage condition exists and comparator C
1
turns discharge transistor MPD on to discharge the output capacitor CL.
The above prior art LDO voltage regulator has several shortcomings. It does not directly detect the presence of an output overvoltage. Instead, it assumes that there is a V
OUT
overvoltage whenever error amplifier A
1
drives the gate of output transistor MPX above V
TRIP
. But that assumption is not necessarily true. For example, if the feedback control loop is optimized for speed, then the output of error amplifier A
1
most likely will exhibit some overshoot in its response to sudden changes in the load current. This could falsely trigger comparator C
1
and cause it to turn on discharge transistor MPD. Even without the above mentioned overshoot on the output of error amplifier A
1
, a rapid decrease in the load current from, for example 100 percent to 50 percent of maximum, may cause comparator C
1
to trip and turn on discharge transistor MPD. While this condition may produce a small overvoltage condition, turning on discharge transistor MPD does not actually help the overall recovery from the load current transient because the remaining load current quickly eliminates the V
OUT
overvoltage condition anyway.
The speed of response of discharge transistor MPD to an overvoltage condition at V
OUT
depends on both the speed of comparator C
1
and the speed of error amplifier A
1
, the output of which is connected to the (−) input of comparator C
1
. Comparator C
1
may be optimized for response speed, but error amplifier A
1
has to drive the large gate capacitance of the large output transistor MPX, and therefore must be optimized for the best overall system operation and compensated for stability. If error amplifier A
1
were infinitely fast, output transistor MPX would turn off before it had time to supply the extra charge into output capacitor CL and create a V
OUT
overvoltage. However, since error amplifier A
1
is not infinitely fast it does introduce significant delay into the response of discharge transistor MPD to a V
OUT
overvoltage event. The delay through error amplifier A
1
cannot be eliminated using the approach of U.S. PAt. No. 5,864,227 because the delay through error amplifier A is in fact the main reason that a V
OUT
overvoltage occurred.
It should be noted that the reference voltage V
TRIP
in prior art
FIG. 1
is unrelated to the V
OUT
overvoltage. Instead, V
TRIP
is set to detect when output transistor MPX is sufficiently turned off that it can be inferred that a V
OUT
overvoltage condition exists. Specifically, the value of V
TRIP
is set using knowledge of a typical amount of V
OUT
overvoltage and the typical characteristics of output transistor MPX, rather than by considering the magnitude of a maximum allowable overvoltage at V
OUT
. The trip voltage V
TRIP
thus is not a function of how far V
OUT
is into an overvoltage condition in order to activate comparator C
1
. Instead, V
TRIP
is determined by the threshold voltage of output transistor MPX and V
CC
.
Furthermore, the LDO voltage regulator of prior art
FIG. 1
is prone to small signal oscillations, wherein the voltage regulator alternately goes into and out of overvoltage correction operation when the output load is zero. This can be understood by considering a rapid load transition of I
OUT
from a heavy load to no load. The regulated output voltage V
OUT
will rise, and the output of error amplifier A
1
will eventually saturate into the V
CC
rail in an attempt to turn off output transistor MPX as much as possible. This activates comparator C
1
, which then turns discharge transistor MPD on to discharge output capacitor CL. The speed and dynamics of the LDO voltage regulator of prior art
FIG. 1
determine how quickly discharge transistor MPD will turn off after V
OUT
reaches its specified value of V
REF
multiplied by (R
1
+R
2
)/R
1
. The same delay through error amplifier A
1
that caused the V
OUT
overvoltage in the first place will also delay the turn off of discharge transistor MPD. During this delay, discharge transistor MPD discharges output capacitor CL to a voltage below the specified value of V
OUT
. V
OUT
then is too low, so error amplifier A
1
slews the gate of output transistor MPX until it turns on enough to increase V
OUT
. Since error amplifier A
1
is recovering from its output being saturated into the V
CC
rail, it is very likely that V
OUT
will overshoot slightly and charge output capacitor CL too much, creating a new V
OUT
overvoltage. Since there is no load drawing current to remove the extra charge of output capacitor CL, the resulting V
OUT
overvoltage remains until the overvoltage correction circuit PD
1
is activated again, and the cycle repeats and creates oscillations of V
OUT
.
Thus, there is an unmet need for an improved LDO voltage regulator which dissipates a reduced amount of power, and does not oscillate under no-load conditions.
SUMMARY OF THF INVENTION
Accordingly, it is an object of the invention to provide an improved LDO voltage regulator which reduces the severity of output overvoltage conditions caused by rapid load current transitions.
It is another object of the invention to provide an improved LDO voltage regulator which both rapidly corrects output overvoltage conditions caused by rapid load current transients and which also dissipates a minimum amount of power in discharging such output overvoltage conditions.
It is another object of the invention to provide an improved LDO voltage regulator which rapidly corrects output overvoltage conditions caused by rapid load current transients and which is not prone to signal oscillations due to alternately going into and out of output overvoltage conditions under no-load conditions.
It is another object of the invention to provide an improved LDO voltage regulator which can correct output overvoltage conditions caused by rapid load current transitions on the basis of the magnitude of the output overvoltage conditions.
It is another object of the invention to provide improved LDO voltage regulator circuitry for correcting output overvoltage conditions which is suitable for use in conjunction with either N-channel or P-c
Heisley David A.
Larson Tony R.
Burr-Brown Corporation
Cahill Sutton & Thomas P.L.C.
Riley Shawn
LandOfFree
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