Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Device protection
Reexamination Certificate
2002-04-04
2003-08-05
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Device protection
C257S355000, C257S360000
Reexamination Certificate
active
06603155
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an overvoltage protection device.
2. Description of the Prior Art
There are in existence a wide range of semiconductor devices which are designed to protect telecommunications equipment from overvoltages which can occur on telephone lines as a result of, for example, lightening strikes and AC power surges. Many of these semiconductor devices are based on a four layer PNPN structure which is designed to switch quickly from a blocking state to a high conduction state when the voltage across the device exceeds a predetermined threshold level.
GB-A-2 113 907 describes a four layered diode (PNPN) semiconductor device which is usable as a transient suppressor because it switches from a high resistance condition to a low resistance condition when the current through it reaches a threshold value. The device has a thyristor type structure with a controlled holding current and an additional buried N-region through which reverse breakdown of the central junction of the structure takes place to control the initial avalanche breakover voltage.
This buried region is of the same conductivity type as the region in which it is formed and has a greater impurity concentration than that region. The effect of the buried region is to cause the reverse voltage breakdown through the central junction to take place through the buried region. This enables the breakdown voltage of the device to be controlled more accurately than is the case in a conventional four layer diode. Although it is not shown in GB-A-2 113 907, the outer layer which acts as the emitter has a number of perforations or dots through it where the material of the adjacent inner layer reaches the surface. The metal contact at the surface produces a resistive short circuit across the junction between the outer and inner layers serving to define the holding current of the device.
In the structure described above the avalanche occurs uniformly across the buried region. The resulting current forward biasses the anode-substrate junction. Similarly, the avalanche current flows via the shorting dots causing a resistive voltage drop thus forward biassing the base-cathode junction and causing the device to latch. Suitable choice of shorting geometry helps to avoid localised switching of the base-cathode junction.
Among the many important characteristics of an overvoltage protection device are the peak voltage before switching occurs, known as the breakover voltage V
BO
, and the maximum voltage below which the device should be operated under normal conditions, known as the forward repetitive maximum voltage V
DRM
. The difference between V
BO
and V
DRM
represents a reduction in the size of the safe voltage window for the equipment and therefore the ratio of V
BO
to V
DRM
should be as close to unity as is possible in order to maximise the operating window for the equipment being protected.
The ability to control the turn on characteristics of such a device not only improves the system protection which the device can provide but in certain applications can improve the power dissipation capability of the device.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved semiconductor overvoltage protection device.
Accordingly, the present invention provides a semiconductor overvoltage protection device in the form of a four layer diode having: first and third layers of a first conductivity semiconductor material; second and fourth layers of a second conductivity type semiconductor material; a first buried region of the first conductivity type in the third layer adjacent to the junction between the second and third layers, the buried region having a greater impurity concentration than the third layer; and a second buried region of the same conductivity type as and of higher impurity concentration than said first buried region in said first buried region adjacent to said junction; wherein: said first layer is penetrated by a plurality of dots of said second layer extending through said first layer; one of said first and second buried regions is formed with a plurality of separate regions of small area arranged so that reverse breakdown of the junction preferentially occurs through said second buried region; and said dots do not overlie portions of said second buried region.
Advantageously, said second buried region is formed with said plurality of separate regions, said regions being laterally offset from said dots.
Advantageously, said first buried region is formed with said plurality of separate regions.
Advantageously, each said dot vertically overlies a respective region of said first buried region.
Advantageously, said second buried region terminates within said first buried region.
Advantageously, said second buried region extends into said first region.
Advantageously, the ratio of impurity concentration in said first and second buried regions is such that the breakdown voltage between said second layer and said first buried region exceeds the breakdown voltage between said second layer and said second buried region by no more than 5%.
Advantageously, one or more of said separate regions has a lateral dimension greater than that of the associated dot.
Advantageously, one or more of said separate regions has a lateral dimension the same as that of the associated dot.
REFERENCES:
patent: 5808342 (1998-09-01), Chen et al.
patent: 5889293 (1999-03-01), Rutten et al.
patent: 6407901 (2002-06-01), Casey et al.
patent: 0700099 (1996-03-01), None
Byatt Steven Wilton
Duane Russell
Smith Jeremy Paul
Abraham Fetsum
Klein O'Neill & Singh, LLP
Power Innovations, Ltd.
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