Overvoltage protection circuit for bidirectional...

Details Overvoltage protection circuit for bidirectional... Overvoltage protection circuit for bidirectional...

2000-12-19

2003-10-14

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

C361S018000, C361S058000, C361S091500, C327S434000

Reexamination Certificate

active

06633470

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to electronic systems and components, and is particularly directed to a new and improved circuit architecture for providing overvoltage protection for a bidirectional transmission gate, particularly one formed of complementary polarity field effect transistors.
BACKGROUND OF THE INVENTION
FIG. 1
diagrammatically illustrates the basic circuit architecture of a conventional complementary polarity FET-based bidirectional transmission gate
10
commonly employed in a variety of electronic circuits and systems for selectively switching analog signals between a first port
11
and a second port
12
. While bidirectional switching allows either port to be employed as an input or an output, for purposes of avoiding confusion in the use of dual terms for both ports, throughout the following present description, port
11
will be designated as an input port IN and port
12
will be designated as an output port OUT.
The complementary polarity FET-configured transmission gate
10
of
FIG. 1
contains a first, N-channel MOSFET (or NMOS) device
20
(a cross-section of which is diagrammatically illustrated in
FIG. 2
) having its (N+) source
21
coupled to input port
11
and its (N+) drain
22
coupled to output port
12
. The P-type body
24
of NMOS device
20
is coupled to its source
21
(by way of an external connection not show in FIG.
2
), and its gate
23
is coupled to a control terminal C. The body-source connection may be represented as a parasitic base connection of a parasitic NPN transistor, shown in broken lines
30
in the device cross-section of
FIG. 2
, and having respective parasitic emitter-base and base-collector pn junctions
31
and
32
of the NMOS device schematic shown in FIG.
3
. To place the NMOS device
20
in the OFF or non-conducting condition the control terminal C is coupled to receive a low logic level switching control voltage such as one corresponding to a negative supply voltage; to place NMOS device
20
in the ON or conducting condition, the control terminal C is coupled to receive a high logic level switching control voltage, such as a positive supply voltage.
The transmission gate
10
of
FIG. 1
further contains a second, P-channel MOSFET (or PMOS) device
40
(a cross-section of which is diagrammatically illustrated in
FIG. 4
) having its (P+) source
41
coupled to input port
11
and its (P+) drain
42
coupled to output port
12
. The N-type body
44
of PMOS device
40
is coupled to its source
41
(as by way of an external connection not shown in FIG.
4
), and its gate
43
is coupled to a control terminal CBAR. The body-source connection can be represented as a parasitic base connection of a parasitic PNP transistor, shown in broken lines
50
in the device cross-section of
FIG. 4
, and having respective parasitic emitter-base and base-collector pn junctions
51
and
52
of the PMOS device schematic shown in FIG.
5
.
To place the PMOS device
40
is the OFF or non-conducting condition, its control terminal CBAR is coupled to receive a high logic level switching control voltage such as one corresponding to a positive supply voltage. To place PMOS device
40
is the ON or conducting condition, its control terminal CBAR is coupled to receive a low logic level switching control voltage, such as a negative supply voltage.
In operation, NMOS device
20
may have a threshold voltage V
NMOS
th=+1V, while PMOS device
40
may have a threshold voltage V
PMOS
th=−1V, with a supply voltage range of +/−15 volts. For an input voltage Vin of +10v applied to input port
11
, and a ground or zero potential coupled to the output port
12
, as diagrammatically illustrated in
FIG. 6
, NMOS device
20
has a Vgs
20
=−25V (−25V<1V), while PMOS device
40
has a Vgs
40
=+5V (+5V>−1V). As a result, each of NMOS device
20
and PMOS device
40
is turned OFF. Namely, the transmission gate
10
can be maintained. in the OFF condition as long as the input voltage falls within the supply voltage range.
On the other hand, for an excessively positive or overvoltage input voltage Vin of +20 v applied to input port
11
, and a ground or zero (0) potential coupled to the output port
12
, as shown diagrammatically in
FIG. 7
, NMOS device
20
has a Vgs
20
=−35V (−35V<1V), so that NMOS device
20
is apparently turned OFF. However, PMOS device
40
has a Vgs
40
=−5V (which is less than −1V), so that PMOS device
40
is undesirably turned ON and provides substantial current flow therethrough. Moreover, even though NMOS device
20
is in the OFF state, the +20 volt applied to the input port
11
is sufficient to forward bias its parasitic base-collector pn junction
32
and provide an additional current leakage path through NMOS device
20
between ports
11
and
12
.
Similarly, for an excessively negative or overvoltage input voltage Vin of −20 v applied to input port
11
, and a ground or zero (0) potential coupled to the output port
12
, shown diagrammatically in
FIG. 8
, the NMOS device
20
has a Vgs
20
=+5V (>+1V), so that the NMOS device
20
is undesirably turned ON, while PMOS device
40
has a Vgs
40
=+35V (which is greater than −1V), so that PMOS device
40
is turned OFF. Although the PMOS device
40
is ostensibly in the OFF state, the −20 volt applied to the input port
11
is sufficient to forward bias its parasitic base-collector pn junction
52
and thereby provide an additional current leakage path through PMOS device
40
between ports
11
and
12
. Thus, the transmission gate
10
fails to remain OFF for an input voltage outside the supply voltage range (regardless of polarity).
FIG. 9
diagrammatically illustrates a modification that may be incorporated into each of the complementary polarity halves of the transmission gate described above, to incorporate a ‘blocking’ diode coupled between the body and a respective supply rail, as well as a complementary MOSFET inverter coupled in circuit between the body and an opposite polarity supply rail. In order to reduce the complexity of the drawings and facilitate the present description, only the PMOS device
40
of the transmission gate will be described. It is to be understood, however, that the description applies equally to the complementary NMOS device
20
for a change in polarity of the parameters of the components and applied voltages.
More particularly, in the modified circuit of
FIG. 9
, a ‘blocking’ diode
45
is installed between the body
44
and a (+15V) positive supply terminal
46
. In addition, a complementary MOSFET inverter
60
comprised of a PMOS transistor
61
and an NMOS transistor
62
, is coupled in circuit between body
44
and a (−15V) negative supply terminal
47
. The gate
43
of PMOS transistor
40
is coupled to the common drain connections of PMOS device
61
and NMOS device
62
, and the common gates of devices
61
and
62
are coupled to a control terminal (to which a logic low input voltage (−15V) is coupled for an OFF condition of the transmission gate). In terms of a practical implementation, an MOS device may be coupled between the diode
45
and the body
44
of the PMOS device
40
for the purpose of isolating the body
44
from the positive supply rail, when the transmission gate is turned ON, in order to connect the transmission gate's NMOS and PMOS bodies together, to provide a flatter on-resistance vs. input voltage caused by the constant body source-voltage allowed by the configuration shown.
For the above parameters, as long as the input voltage remains within the supply voltage range (+/−15V), the transmission gate can be controllably maintained in the OFF condition. (As shown in
FIG. 10
, the parasitic PNP transistor
50
will also remain OFF, with both emitter-base and base-collector PN junctions being reverse-biased, so that the parasiti

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