Overvoltage and electrostatic discharge protection for a receive

Details Overvoltage and electrostatic discharge protection for a receive Overvoltage and electrostatic discharge protection for a receive

1998-09-18

2000-04-11

Gaffin, Jeffrey

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 915, 327328, H02H 904

Patent

active

06049445&

ABSTRACT:
A receiver circuit that is substantially insensitive to overvoltage and electrostatic discharge (ESD) conditions. The receiver circuit includes a pass transistor having an input side for receiving a signal, an output side, and a gate susceptible to damage when an ESD potential is present. A receiver is coupled to the output side of the pass transistor to receive the signal. A first protection circuit has a first rail, providing an operating voltage potential to the gate of the pass transistor, and structure that electrically decouples the first rail from the gate of the pass transistor. The first protection circuit provides (1) the operating voltage potential to the gate when an ESD potential is not present, and (2) a voltage which tracks the ESD potential when the ESD potential is present at the input side of the pass transistor. A second protection circuit has a first mechanism for providing a test signal voltage to the output side of the pass transistor and a second mechanism for electrically decoupling the output side of the pass transistor. The second protection circuit provides (1) the test signal voltage to the output side of the pass transistor when an ESD potential is not present, and (2) a voltage which tracks the ESD potential when the ESD potential is present at the input side of the pass transistor. A resistor and a clamping transistor may also be added to the receiver circuit to provide additional robust structure guarding against overvoltage or ESD conditions.

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