Oversampling clock recovery circuit

Details Oversampling clock recovery circuit Oversampling clock recovery circuit

2001-05-03

2002-09-24

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S144000

Reexamination Certificate

active

06456128

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock recovery circuit for extracting a clock from inputted data, and more particularly to an oversampling clock recovery circuit for sampling transmitted data with a plurality of clocks that are out of phase with each other.
2. Description of the Related Art
In recent years, there has been proposed a high-speed protocol for the transmission of data. In view of the proposed high-speed protocol, there are demands for high-speed clock recovery circuits for extracting a clock from data transmitted at a high rate, or high-speed phase-locked loops (PLL) for synchronizing the frequency of a clock used within a circuit with the frequency of a clock transmitted to the circuit.
One conventional analog clock recovery circuit uses a single-phase clock whose each positive-going edge is associated with one-bit data for phase comparison. According to the conventional analog clock recovery circuit, since the data rate and the clock frequency need to be equal to each other, if the data rate is at a Gbps level, then it is necessary that the clock frequency be a high frequency at a GHz level. It has been difficult to meet demands for high-speed clock recovery circuits and high-speed phase-locked loops. For example, it is not easy to increase the oscillation frequency of a voltage-controlled oscillator (VCO) included in a phase-locked loop to a high frequency at a GHz level.
In order to meet the above demands, there has been proposed an oversampling clock recovery circuit for sampling transmitted data with a plurality of clocks that are out of phase with each other which have a frequency lower than the rate of data generated within the circuit. The proposed oversampling clock recovery circuit associates a plurality of positive-going edges of the clocks with one-bit data for phase comparison. The oversampling clock recovery circuit can meet the demands for high-speed clock recovery circuits because it uses clocks having a frequency lower than the data rate.
For oversampling data at twice the sampling rate with a clock frequency that is one-half of the data rate, as shown in
FIG. 1A
of the accompanying drawings, four-phase clocks CLK
1
through CLK
4
are used. For oversampling data at twice the sampling rate with a clock frequency that is one-eighth of the data rate, as shown in
FIG. 1B
of the accompanying drawings, 16-phase clocks CLK
1
through CLK
16
are used.
In the oversampling clock recovery circuit, a voltage-controlled oscillator generates a predetermined number of clocks (hereinafter referred to as “multiphase clocks”) required for phase comparison, as disclosed in Japanese laid-open patent publication No. 10-4349 and U.S. Pat. No. 5,694,062.
An oversampling clock recovery circuit in which multiphase clocks are generated by a voltage-controlled oscillator will be described below with reference to
FIG. 2
of the accompanying drawings.
FIG. 2
is a block diagram of conventional oversampling clock recovery circuit
40
, which performs phase comparison using 16-phase clocks.
In conventional oversampling clock recovery circuit
40
, voltage-controlled oscillator
41
includes voltage-controlled delay line
42
comprising a cascaded array of eight differential buffers, and generates 16-phase clocks (differential 8 clock phases) while performing frequency and phase modulation.
Signal processor
13
is supplied with the 16-phase clocks from voltage-controlled oscillator
41
and extracts clocks for an oversampling process. Signal processor
13
has eight phase detectors PD
2
each for carrying out phase comparison between successive three-phase clocks of the 16-phase clocks and inputted serial data. If the clocks lag the inputted serial data, then each of phase detectors PD
2
outputs an UP signal. If the clocks lead the inputted serial data, then each of phase detectors PD
2
outputs a DOWN signal. Based the UP signal or DOWN signal (phase difference information), signal processor
13
generates control voltage V
4
suitable for bringing the clocks into phase with the inputted serial data, and applies generated control voltage V
4
to voltage-controlled oscillator
41
. Thus, voltage-controlled oscillator
41
is feedback-controlled to modulate the frequency and phase of the clocks again based on control voltage V
4
in order to bring the clocks into phase with the inputted serial data, thus generating 16-phase clocks that are supplied to signal processor
13
. In
FIG. 2
, control voltage V
4
is generated by signal processing circuit
15
, charge pump CP
2
, and low-pass filter LPF
2
, for example. Signal processing circuit
15
comprises a majority circuit, an averaging circuit, etc.
Converters CV
1
converts the multiphase clocks from a differential signal into a single-phase signal and also converts them from a small amplitude to a large amplitude before the multiphase clocks are supplied to signal processor
13
.
If clock recovery circuit
40
is supplied with 2.5 Gbps serial data, then clock recovery circuit
40
uses a clock frequency of 312.5 MHz (a period of 3200 ps), and each of the differential buffers of voltage control delay line
42
has a propagation delay time of 200 ps. Therefore, clock recovery circuit
40
generates 16-phase clocks that are successively out of phase by 200 ps.
The conventional clock recovery circuit has suffered the following problems:
In the conventional clock recovery circuit, the voltage-controlled oscillator is controlled to achieve phase synchronization. Therefore, in the process of phase control, the frequency is necessarily caused to fluctuate, making jitter characteristics poor and lowering the quality of the clocks.
The conventional clock recovery circuit also suffers a problem when applied to a transceiver having a number of serial input/output channels.
For example, if conventional clock recovery circuits
40
are provided in respective channels as shown in
FIG. 3
of the accompanying drawings, then a number of voltage-controlled oscillators
41
are present on an IC chip. Voltage-controlled oscillators
41
on the IC chip tend to resonate between the channels, making jitter characteristics poor and lowering the quality of the multiphase clocks. Furthermore, since the voltage-controlled oscillators generally have a large power consumption requirement, the overall chip consumes a large amount of electric energy.
If one voltage-controlled oscillator is shared by a number of channels to supply multiphase clocks to the channels, then difficulty arises in supplying the multiphase clocks to the channels. In the process of supplying the multiphase clocks to the channels, the multiphase clocks are degraded to different extents for the different phases, resulting in a reduction in the quality of the multiphase clocks. An arrangement wherein one voltage-controlled oscillator is shared by a number of channels to supply multiphase clocks to the channels will be described below with reference to
FIG. 4
of the accompanying drawings.
As shown in
FIG. 4
, channels ch
1
through ch(n) are associated respectively with oversampling clock recovery circuits
60
(
1
) through
60
(n) each having signal processor
13
and phase control circuit
11
. Single phase-locked loop
50
including voltage-controlled oscillator
51
generates multiphase clocks (16-phase clocks in
FIG. 4
) and supplies the generated multiphase clocks to respective oversampling clock recovery circuits
60
(
1
) through
60
(n). Channels ch
1
through ch(n) are not associated with respective voltage-controlled oscillators, but receive the multiphase clocks from phase-locked loop
50
and performs phase control between the multiphase clocks and inputted data.
Since the single voltage-controlled oscillator is shared by the many channels, the system shown in
FIG. 4
is free of drawbacks that would be caused if a number of voltage-controlled oscillators were present on one IC chip.
However, since phase-locked loop
50
is required to supply multiphase clocks to many channels ch
1
through ch(n), it suf

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