Oversampling circuit and method

Details Oversampling circuit and method Oversampling circuit and method

2001-10-22

2002-07-16

Tokar, Michael (Department: 2816)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C326S113000, C327S415000, C327S416000, C341S079000, C341S100000, C341S101000

Reexamination Certificate

active

06420981

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90117175, filed Jul. 13, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention:
This invention relates to signal processing technology, and more particularly, to an oversampling circuit and method.
2. Description of Related Art:
Serial link technology is utilized in communications systems, can offer a data transmission rate up to one billion bits per second and is also low cost to implement. Due to these benefits, the serial link technology is widely used in radio transceivers, computer-to-computer communication, and computer-to-peripheral communication.
FIG. 1
shows a conventional transceiver which utilizes serial link technology (for details, please refer to IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. MAY 5, 1988, “A 0.5 &mgr;m CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery (Using Oversampling”, Chih-Kong Ken Yan, Ramin Farjad-Rad, Mark A. Horowitz). As shown, the transceiver
100
includes an oversampling circuit
102
whose input end (Data In) is used to receive a 4-Gbps serial data stream, and which is capable of converting the serial data into 8-bit parallel format. In order to obtain the correct transition of each bit, the oversampling circuit
102
utilizes a sampling rate three times the bit rate of the input data. Therefore, the PLL (phase-locked loop) circuit
104
should output 24 sampling pulses to the oversampling circuit
102
for each output byte.
FIG. 2
shows a conventional oversampling circuit
200
(which can be used to serve as the oversampling circuit
102
shown in FIG.
1
). As shown, this oversampling circuit
200
includes 24 MOSFETs, each MOSFET has a gate connected to the PLL circuit
104
shown in
FIG. 1
to receive one of the 24 output sampling pulses from the PLL circuit
104
; i.e., the first MOSFET
202
has its gate connected to receive the first sampling pulse &PHgr;
1
from the PLL circuit
104
; the second MOSFET
204
has its gate connected to receive the second sampling pulse &PHgr;
2
; and so forth the last MOSFET
206
having its gate connected to receive the 24th sampling pulse &PHgr;
24
.
Referring back to
FIG. 1
, since the input end (Data In) of the oversampling circuit
102
receives a 4-Gbps serial data stream, the period of each bit is 250 ps (picosecond). Therefore, the use of the triple sampling rate would result in a phase difference &Dgr;t as follows:
&Dgr;
t
=250/3=83
ps
The pulse sequencing diagram of the sampling pulses (&PHgr;
1
~&PHgr;
24
is shown in FIG.
3
. The period T of each of the sampling pulses &PHgr;
1
~&PHgr;
24
is 250 ps, and the phase difference between two successive sampling pulses is &Dgr;t=83 ps. These 24 sampling pulses &PHgr;
1
~&PHgr;
24
are used for the sampling of one byte of data; wherein the first three sampling pulses &PHgr;
1
~&PHgr;
3
are used for the sampling of the first bit in the byte, the second three sampling pulses &PHgr;
4
~&PHgr;
6
are used for the sampling of the second bit in the byte, and so forth the last three sampling pulses &PHgr;
22
~&PHgr;
24
being used for the sampling of the eighth bit in the byte.
Therefore, one byte of data is generated for each cycle of the 24 sampling pulses &PHgr;
1
~&PHgr;
24
.
Each cycle of the 24 sampling pulses &PHgr;
1
~&PHgr;
24
will respectively cause the 24 transmission gates of the MOSFETs in the oversampling circuit
200
of
FIG. 2
to be switched ON. In this case, the fan-out loading of the oversampling circuit
200
is the loading of the 24 transmission gates. If the sampling rate is five times the bit rate, the oversampling circuit then needs 40 transmission gates; and in this case, the fan-out loading is the loading of the 40 transmission gates. Fundamentally, a larger sampling rate will require a larger fan-out loading. However, an overly large fan-out loading would cause the oversampling circuit to lose its fan-out capability.
One solution to the foregoing problem is to use a multi-stage oversampling circuit
400
shown in
FIG. 4
, which needs 27 sampling pulses rather than 24 for each cycle of byte. As shown, these 27 sampling pulses are denoted by (&PHgr;
1,1
~&PHgr;
1,8
, &PHgr;
2,1
~&PHgr;
2,8
, &PHgr;
3,1
~&PHgr;
3,8
, &PHgr;
F1
~&PHgr;
F3
); wherein &PHgr;
1,1
~&PHgr;
1,8
are applied to the respective gates of 8 MOSFETs (
401
,
402
, . . . ,
403
); &PHgr;
2,1
~&PHgr;
2,8
are applied to the respective gates of 8 MOSFETs (
405
,
406
, . . . ,
407
); &PHgr;
3,1
~&PHgr;
3,8
are applied to the respective gates of 8 MOSFETs (
409
,
410
, . . . ,
411
); and &PHgr;
F1
~&PHgr;
F3
are applied to the respective gates of 3 MOSFETs (
404
,
408
, . . . ,
412
). This requires the PLL circuit
104
to generate 27 sampling pulses.
FIG. 5
shows the pulse sequencing diagram of the 27 sampling pulses &PHgr;
1,1
~&PHgr;
1,8
, &PHgr;
2,1
~&PHgr;
2,8
, &PHgr;
3,1
~&PHgr;
3,8
and &PHgr;
F1
~&PHgr;
F3
. As shown, the period T of each of the 27 sampling pulses is T=250 ps, and the phase difference between two successive pulses in &PHgr;
1,1
~&PHgr;
1,8
, &PHgr;
2,1
~&PHgr;
2,8
and &PHgr;
3,1
~&PHgr;
3,8
is &Dgr;t
1
=83 ps. The sampling pulse &PHgr;
F1
appears at logic-HIGH state for a period of 7*&Dgr;t
1
+&Dgr;t
2
, which causes the MOSFET
404
to be switched ON. Then, the 8 MOSFETs (
401
,
402
, . . . ,
403
) are successively switched ON by &PHgr;
1,1
~&PHgr;
1,8
, allowing them to sample the input serial data. The sampling pulse &PHgr;
F1
is switched from logic-HIGH back to logic-LOW by a time lag of &Dgr;t
2
after the transition of the last sampling pulse &PHgr;
1,8
from logic-LOW to logic-HIGH. This can help ensure that the last MOSFET
403
has been switched ON when the MOSFET
404
is switched OFF.
After &PHgr;
F1
has been switched from logic-HIGH to logic-LOW, &PHgr;
F2
must be switched from logic-LOW to logic-HIGH at an earlier time than or at the same time as &PHgr;
2,1
. This can help prevent the condition of the MOSFET
405
being switched ON while the MOSFET
408
is still in OFF state. Otherwise, it would cause loss of data at the MOSFET
405
. Therefore, &PHgr;
F2
should remain at logic-HIGH for a period of 7*&Dgr;t
1
+&Dgr;t
2
(the same as &PHgr;
F1
).
When the sampling pulse &PHgr;
F2
appears at logic-HIGH, it causes the MOSFET
408
shown in
FIG. 3
to be switched ON. Then, the 8 MOSFETs (
405
,
406
, . . . ,
407
) are successively switched ON by &PHgr;
2,1
~&PHgr;
2,8
allowing them to sample the input serial data. The sampling pulse &PHgr;
F2
is switched from logic-HIGH back to logic-LOW by a time lag of &Dgr;t
2
(&Dgr;t
2
<&Dgr;t
1
) after the transition of the last sampling pulse &PHgr;
2,8
from logic-LOW to logic-HIGH. This can help ensure that the last MOSFET
407
has been switched ON when the MOSFET
408
is switched OFF.
The operations of the sampling pulses (&PHgr;
3,1
~&PHgr;
3,8
, &PHgr;
F3
) are similar to the operations of (&PHgr;
1,1
~&PHgr;
1,8
, &PHgr;
F1
) and (&PHgr;
2,1
~&PHgr;
2
2,8
, &PHgr;
F2
), so description thereof will not be repeated.
The forgoing multi-stage oversampling circuit
400
shown in
FIG. 4
can solve the earlier-mentioned fan-out problem of the conventional oversampling circuit by providing an additional stage of MOSFET circuit, i.e., the three MOSFETs
404
,
408
,
412
. This first stage of MOSFET circuit (
404
,
408
,
412
) can separate the input end (Data In) from the second stage of MOSFET circuit [(
401
,
402
, . . . ,
403
), (
405
,
406
, . . . ,
407
), (
409
,
410
, . . . ,
411
)], thus allowing the outputs of the first stage of MOSFET circuit to be directly fan-out to the output loading of the second stage of MOSFET circuit.
One drawback to the forgoing multi-stage oversampling circuit
400
shown in
FIG. 4
, however, is that the timing for the sampling pulse used to switch the first stage of MOSFET circuit and the second stage of MOSFET circuit should be highly precisely controlled; otherwise, if any of the MOSFET in the first stage slig

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