Overload protection circuit for MOS power drivers

Details Overload protection circuit for MOS power drivers Overload protection circuit for MOS power drivers

1995-03-21

1998-05-05

Nguyen, Matthew V.

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

361 18, G05F 1569, H02H 700

Patent

active

057479755

ABSTRACT:
The circuit includes two regulating loops connected in parallel to each other. A slow regulating loop presents a lower first intervention threshold, and a fast regulating loop has a higher second intervention threshold. The slow regulating loop is low-gain and frequency-stable for accurately controlling the maximum value of the current supplied by the driver in the event of slow overloads or transient states. In the event of rapid overloads, the current supply increases rapidly and the fast regulating loop is turned on to rapidly discharge the parasitic capacitance of the driver.

REFERENCES:
patent: 4785207 (1988-11-01), Eng
patent: 4808839 (1989-02-01), Dunn et al.
patent: 4809122 (1989-02-01), Fitzner
patent: 4972136 (1990-11-01), Banura
patent: 5172018 (1992-12-01), Colandrea et al.
patent: 5282107 (1994-01-01), Balakrishnan
patent: 5499152 (1996-03-01), Tamakoshi
European Search Report from European Patent Application No. 94830125.4, filed Mar. 22, 1994.
Patent Abstracts of Japan, vol. 14, No. 533 (E-1005) Nov. 22, 1990 & JP-A-02 224 521 Mitsubishi Electric Corporation.

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