Overlay test measurement systems

Photocopying – Miscellaneous

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324158R, 430 5, G03B 4300

Patent

active

044758111

ABSTRACT:
This invention relates to overlay test measurement systems which are useful for testing lithographic instruments used in making microcircuits, which includes a single second-level pattern set in the middle of a checkerboard-like arrangement of first level patterns alternating with opaque patterns, the patterns being constructed and arranged so that if a second substantially identical cluster is imaged on the first cluster with the second level pattern of the second cluster aligned with any one of the first level patterns on the first cluster then the opaque patterns of the second cluster would be aligned with the other first level patterns on the first cluster thereby protecting them from exposure.
According to a feature of the invention there is provided a method of making a test wafer of the type described as well as a method of testing the alignment of lithographic tools using the aforesaid test mask and test wafer.

REFERENCES:
patent: 3743417 (1973-07-01), Smatlak
patent: 3771872 (1973-11-01), Nightingale et al.
patent: 3873203 (1975-03-01), Stevenson
patent: 3914050 (1975-10-01), Dost et al.
patent: 4286871 (1981-09-01), Erickson
SPIE, vol. 334, Optical Microlithography Tech. for Mid 1980s, (1982), "Variable Magnification in a 1:1 Projection Lithography System", pp. 2-9, James J. Greed, Jr., David A. Markle.
Technical Digest, 1977 International Electron Devices Meeting, Dec. 5-7, (1977), pp. 7-7F, "A Comparison of Electrical and Visual Alignment Test Structures for Evaluation Photomask Alignment in Integrated Circuit Manufacturing", T. J. Russell et al.
IEEE Transactions of Electron Devices, vol. ED-26, No. 4, Apr. 1979, "Automatic Testing and Analysis of Misregistrations Found in Semiconductor Processing", pp. 729-732, Ivor J. Stemp et al.
Solid State Technology/May 1981, "Microelectric Test Structures for Characterizing Fine-Line Lithography, pp. 126-140, D. S. Perloff et al.
Solid State Technology/Sep. 1980, "Use of Microelectronic Test Structures to Characterize IC Materials, Processes, and Processing Equipment", G. P. Carver et al.
Solid State Technology/Feb. 1980, "Real-Time Monitoring of Semiconductor Processes Uniformity", pp. 81-86, D. S. Perloff et al.
Solid State Science and Technology/Mar. 1981, "Alignment, and Mask Errors in IC Processing, pp. 609-614, K. H. Nicholas et al.
Fifteenth Symposium on Electron Ion and Photon Beam Technology, Boston, May 1979, "Performance Limits in 1:1 UV Projection Lithography", pp. 26-34, J. H. Bruning.

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