Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2001-08-10
2003-03-11
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S462000, C257S622000, C257S797000
Reexamination Certificate
active
06531374
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the deposition of epitaxial silicon layers in semiconductor processing, and particularly to the deposition of further layers on top of such epitaxial silicon layers.
BACKGROUND OF THE INVENTION
Patterning is one of the basic steps performed in semiconductor processing. It also referred to as photolithography, masking, oxide or metal removal, and microlithography. Patterning enables the selective removal of material deposited on a semiconductor substrate, or wafer, as a result of a deposition process. For example, as shown in
FIG. 1A
, a layer
104
has been deposited on a substrate
102
. After the photolithography process is performed, as shown in
FIG. 1B
, some parts of the layer
104
have been selectively removed, such that gaps
106
a
and
106
b
are present within the layer
104
. A photomask, or pattern, is used (not shown in
FIG. 1B
) so that only the material from the gaps
106
a
and
106
b
are removed, and not the other portions of the layer
104
. The process of adding layers and removing selective parts of them, in conjunction with other processes, permits the fabrication of semiconductor devices.
Alignment is critical in photolithography and deposition, as well as in other semiconductor processes. If layers are not deposited properly, or if they are not selectively removed properly, the resulting semiconductor devices may not function, relegating them to scrap, which can be costly. Therefore, alignment marks are placed on the semiconductor wafer for the photomask used in photolithography to be correctly positioned thereover. This is shown in
FIG. 2
, where the semiconductor wafer
202
has alignment marks, such as the alignment square
204
, thereon. When the photomask
206
is positioned over the wafer
202
, its own alignment marks, such as the alignment square
208
, is aligned with the alignment marks of the wafer
202
. For example, the alignment square
208
of the photomask
206
is aligned so that the alignment square
204
of the wafer
202
is centered therein.
The use of a mask in photolithography and deposition presumes that more than one semiconductor device is processed at a time. That is, using a mask means that all, or a substantial portion, of the semiconductor wafer, with its constituent semiconductor device areas, is processed at a time. In other instances, however, processing in general, and photolithography and deposition in particular, is performed on a device-by-device basis on the wafer.
This is accomplished with equipment called a stepper, which steps from one device to another on the semiconductor wafer, performing the same processing step on each device. For example, as shown in
FIG. 3
, processing may be performed by a stepper on the wafer
302
first relative to device
1
, then to device
2
, and so on, until device
12
is reached. Rather than using a mask, a stepper uses a reticle, which is a mask for only a portion, such as a single device, of a wafer. Alignment is especially critical when using a stepper, because each time the stepper steps to a new device, the reticle must be properly aligned with the underlying device.
While many different types of materials can be deposited on silicon wafers, one type of material that is frequently deposited is epitaxial silicon, or “epi.” Epitaxial, or “epi,” silicon layers frequently need to be deposited on the substrate before other layers of other materials are deposited. Epitaxial silicon is a single crystalline structure of film, which comes about when silicon atoms are deposited on a bare silicon wafer in a chemical vapor deposition (CVD) reactor. The use of epitaxial silicon allows for the fabrication of different types of semiconductor devices.
However, deposition of an epi silicon layer frequently obscures the underlying alignment marks on the silicon wafer, which can mean that the epi layer itself, as well as the subsequent layers, become misaligned. Misalignment is also referred to as overlay shift. This is shown in FIG.
4
. The epi layer
404
may or may not be deposited in a properly aligned configuration on the substrate
402
. However, because the epi layer
404
obfuscates alignment marks
408
on the substrate
402
, subsequent deposition layers
406
a,
406
b
, . . . ,
406
n
are misaligned. This is indicated by the reference marks
410
a,
410
b
, . . . ,
410
n,
which are shown in
FIG. 4
for illustrative clarity only. The reference marks
410
a,
410
b
, . . . ,
410
n,
should substantially align over the alignment marks
408
of the substrate
402
, but they do not.
Misalignment is a serious problem, especially in the fabrication of image sensor integrated circuits (IC's), and mixed signal IC's, the latter which may result from either bipolar or bipolar complementary metal oxide semiconductor (BiCMOS) processing. The semiconductor engineer or technician responsible for the fabrication may have to manually align post-epi layers to ensure that overlay shift does not occur. This is a time-intensive, and therefore costly, undertaking, and still results in significant semiconductor wafer scrap. Wafer scrap can sometimes be reused, but often is discarded, resulting in added costs incurred by the semiconductor foundry. Furthermore, where the foundry customer requests a new mask to be used for one or more of the layers, the engineer or technician must expend even more effort to ensure that overlay shift does not occur.
A solution to this problem is to add alignment marks to the first post-epi layer deposited. However, this adds an extra process step to the device fabrication process, and therefore is disadvantageous because it adds cost and time to fabrication. Therefore, there is a need for preventing overlay shift, or misalignment, of epitaxial silicon layers and post-epitaxial silicon layers deposited on a semiconductor substrate. There is a need for such misalignment correction without resulting in significant wafer scrap, and without requiring significant effort by the engineer or technician to perform the correction. There is also a need for overlay shift correction without having to add alignment marks to post-epi deposition layers. For these and other reasons, there is a need for the present invention.
SUMMARY OF THE INVENTION
The invention relates to correcting overlay shift of an epitaxial silicon layer deposited on a semiconductor wafer, and of post-epitaxial silicon layers subsequently deposited. When an epitaxial silicon layer of a given thickness is deposited, the zero mark coordinates for the deposition are shifted relative to alignment marks on the wafer by a distance based on the thickness of the layer. The distance is preferably proportional to the thickness of the epi layer. This prevents overlay shift of the epi layer. For post-epitaxial silicon layers subsequently deposited, preferably except for the first post-epi layer, a clear out process is initially performed to maintain the alignment marks on the semiconductor wafer. In this way, overlay shift, or misalignment, of the post-epi layers is also prevented.
The invention provides for advantages over the prior art. Wafer scrap is significantly reduced, because the invention corrects overlay shift, or misalignment, of the epitaxial silicon layer and subsequently deposited layers. The invention is performed without significant effort expended by the semiconductor engineer or technician to perform the correction. Preferably, for instance, the zero mark coordinates shift of the epitaxial silicon layer deposition, and the clear out process performed prior to subsequent deposition of post-epi layers, can be programmed in the stepper job file of the stepper performing the operation. This programming can be accomplished without requiring an extra processing step for the stepper to perform. The invention also does not require the addition of alignment marks to the post-epi layers to prevent overlay shift, as is required by the prior art.
Still other embodiments, aspects, and advantages of the invention will become apparent by reading th
Chen Hung-Chih
Lee Kun-I
Leu Ren-Jyh
Wu Tai-Yuan
Le D
Nelms David
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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