Measuring and testing – Surface and cutting edge testing – Roughness
Reexamination Certificate
2000-08-25
2003-09-02
Niebling, John F. (Department: 2812)
Measuring and testing
Surface and cutting edge testing
Roughness
Reexamination Certificate
active
06612159
ABSTRACT:
FIELD OF THE INVENTION
This invention is directed toward a measurement technique used in the manufacture of semiconductor wafers and, more particularly, to determine the registration of overlying semiconductor layers with each other.
BACKGROUND OF THE INVENTION
The fabrication of complex semiconductor devices on wafers, typically made of silicon, involves multiple processing steps which produce several overlying layers of different materials. The several layers contain corresponding features designed to cooperate with each other. Displacement between corresponding features on different layers can degrade device performance or can cause the devices to be totally inoperative. Consequently, the wafer layers must be precisely registered, or accurately aligned in stacked position relative to each other, to enable proper operation of each device in accordance with its design. As semiconductor devices have become increasingly complex, the dimensions of the features have been correspondingly reduced. This reduction in feature dimensions has reduced acceptable tolerances on displacement between layers. It is standard practice to set the acceptable tolerance at one-third of the process critical line width. For example, in current 0.18 micron technology, the tolerance is 0.06 micron (60 nanometers).
Since such wafers are expensive to fabricate, it is desirable to measure the overlay registration error (sometimes referred to hereinafter as the “error”) after each lithography process, i.e. after the application, or printing, of each layer onto the wafer, in order to verify that the printed layer is in registration with the previous layer within acceptable tolerances. If the error is outside of the acceptable tolerances, the defective layer can, in some cases, be removed and replaced with an accurately registered layer after the fabrication equipment is suitably adjusted based on the measured error. In other cases, the wafer is scrapped, thereby saving the expense of conducting further processing steps on defective wafers. Also, based on such error measurements, it is possible to collect statistical process control (“SPC”) data to track the overlay registration errors over time for use in controlling the wafer fabrication process.
A lithography tool is a machine which is essential to wafer fabrication. It places the designed image on the wafer. One such lithography tool is a stepper. For ease of explanation, the word stepper is used herein to represent all types of lithography tools. A stepper places the designed image on the wafer in an array of stepper fields. Each stepper field can include, for example, an array of dies that will be made into electronic components when the wafer is cut along scribe lines. To assist in overlay verification measurements, also known as in-process metrology, it has been common practice to provide each stepper field with a number of registration marks, or targets. For example, a target can be placed in each corner of the stepper field and perhaps another one in its interior area. One version of such a target, known as the “box in box”, is shown in
FIGS. 1 and 2
. Target
1
on wafer
3
includes patterns
5
and
9
formed on layers
7
and
11
, respectively. For example, “inner” pattern
5
is usually a solid square of photoresist, and “outer” pattern
9
is usually formed on a substrate layer. Typically, pattern
5
is a 10 micron square and pattern
9
is a 20 micron square.
Other versions of the target are known as “frame in frame” (see
15
in
FIG. 3
) and “bar in bar” (see
17
in FIG.
4
). These are substantially the same in that the corners of target
15
are left out to form target
17
. More specifically, outer pattern
19
of target
15
is a set of segments
21
-
24
joined together to form a continuous wall
15
A. Outer pattern
19
′ of target
17
is a set of segments
21
′-
24
′ which are not joined to each other. A cross section of both targets is shown in FIG.
5
. Pattern
5
in
FIGS. 3 and 4
can be the same solid pattern as shown in
FIGS. 1 and 2
. Alternatively, it can be a frame or a bar pattern also.
The word “pattern” as used herein broadly refers to any geometric shape that is recognizable by an automated metrology system for the purpose of making overlay registration measurements. The shape can be the external periphery of one body, such as solid square
5
, or it can be defined by a plurality of bodies, connected to each other or not, such as the segments
21
-
24
and
21
′-
24
′.
Automated metrology systems for performing a two-layer overlay registration error measurement are well known. Such a system generates an optical image of the target which is recorded by a CCD camera, and the image is digitized. The digitized image is processed to determine the center position of a pattern. A standard technique for center measurement used in two-layer overlay registration error measurements is to locate the edges of the pattern. There are a number of well known algorithms available to do this, such as pure centroid (center of gravity) and best fit calculations. Once the edges have been located, and since the patterns of the two-layer targets are defined as having a square shape, the center is the direct average of the two horizontal (for y value) and vertical (for x value) edge locations. Such a technique, known as “Smart Plus”, is used in the model IVS 120 system available from Schlumberger Verification Systems in Concord, Mass. The portion of the IVS 120 User's Manual relevant to this technique is hereby incorporated by reference.
The overlay registration error between two layers is determined by calculating the difference between the center of the outer pattern and the center of the inner pattern. Once the centers of both patterns are known, the overlay registration error is determined by subtracting the inner pattern center from the outer pattern center. This can be expressed by the following relationship:
Overlay Registration Error=(Or−Ol)−(Ir−Il), (Ob−Ot)−(Ib−It)
where
Or is the x value for the outer pattern right edge;
Ol is the x value for the outer pattern left edge;
Ob is the y value for the outer pattern bottom edge;
Ot is the y value for the outer pattern top edge;
Ir is the x value for the inner pattern right edge;
Il is the x value for the inner pattern left edge;
Ib is the y value for the inner pattern bottom edge;
It is the y value for the inner pattern top edge.
This derived error is expressed as x,y values that can be mapped onto a statistical plot which displays the limits of the acceptable tolerances. By plotting the x,y values of the derived error, the stepper operator can readily determine whether or not the process is within spec (i.e. the acceptable tolerances have not been exceeded). Moreover, the plotted results may even assist in guiding the operator to make the necessary adjustment in re-applying the defective layer to avoid a repetition of the misregistration. Various types of such plots, as well as diagrams, charts and tables used for process control purposes, are well known and in conventional usage, and selecting a particular one is a matter of design choice.
Automated techniques are also available to provide pass/fail/adjust data based on the two-layer overlay registration measurement error. The error value is used as an input which results in a stepper correction being generated automatically. One such technique is described in a paper by Edward A. Mc Fadden and Christopher P. Ausschnitt titled “A Computer Aided Engineering Workstation for Registration Control”, published in SPIE Vol. 1087 of Integrated Circuit Metrology, Inspection, and Process Control III (1989), pages 255-266. This paper is hereby incorporated by reference.
It is not sufficient to measure only the overlay between two layers to insure that they are within the acceptable tolerances because for some layer combinations the overlay is critical among more than just two layers (referred to broadly hereinafter as “multi-layer” overlay). As is well known, one su
Cohen & Pontani, Lieberman & Pavane
Niebling John F.
Schlumberger Technologies Inc.
Stevenson André C
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