Patent
1976-04-19
1978-08-15
James, Andrew J.
357 15, 357 71, H01L 2980, H01L 2948, H01L 2956
Patent
active
041077202
ABSTRACT:
A high-frequency, high-power FET constructed upon a planar substrate with a repeated pattern of gate, source, and drain connections wherein any two are interconnected with metallization layers adjacent to and separated from the semiconductor substrate. The third element is interconnected with an overlay metallization layer separated from the lower two metallization layers by an insulating dielectric. The overlay layer is preferably grounded for minimum feedback capacitance.
REFERENCES:
patent: 3657615 (1972-04-01), Driver
patent: 3737743 (1973-06-01), Goronkin et al.
patent: 3783349 (1974-01-01), Beasom
patent: 3822467 (1974-07-01), Symersky
patent: 3967305 (1976-06-01), Zuleeg
patent: 3969745 (1976-07-01), Blocker
patent: 4005467 (1977-01-01), Vergnolle
patent: 4015278 (1977-03-01), Fukuta
Proceeding IEEE, vol. 59, No. 5, May 1971, A Proposed Vertical Channel Variable Resistance FET, pp. 805-807.
RCA Review, vol. 32, Dec. 1971, Switching Times of a Moderate Power GaAs FET, pp. 645 to 649.
Benjamin James A.
Pucel Robert A.
Bartlett Milton D.
Inge John R.
James Andrew J.
Pannone Joseph
Raytheon Company
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