Overlay measuring method using correlation function

Details Overlay measuring method using correlation function Overlay measuring method using correlation function

1997-02-26

1999-03-02

Dutton, Brian

Semiconductor device manufacturing: process

With measuring or testing

Optical characteristic sensed

438401, 355 53, H01L 2166, H01L 2176, G01R 3126, G03B 2742

Patent

active

058770364

ABSTRACT:
In a method of manufacturing a semiconductor integrated circuit device, a resist pattern is formed on a lower layer pattern of a semiconductor substrate using a mask. An image signal along a line extending on the lower layer pattern and the resist pattern is generated by an optical system. Based on the image signal, a center position of the resist pattern and a center position of the lower layer pattern are calculated using correlation calculation and an overlay error of the resist pattern to the lower layer pattern is determined. When the overlay error falls within a predetermined range, a next manufacturing process such as an etching process and an ion implantation process to the semiconductor substrate is executed. When the overlay error does not fall within a predetermined range, the resist pattern is removed, and a relative position between the semiconductor substrate and the mask is adjusted. Thereafter, the above steps are repeated.

REFERENCES:
patent: 4441206 (1984-04-01), Kuniyoshi et al.
patent: 4679942 (1987-07-01), Suwa et al.
patent: 5438413 (1995-08-01), Mazor et al.
patent: 5468580 (1995-11-01), Tanaka
patent: 5493403 (1996-02-01), Nishi
patent: 5543921 (1996-08-01), Uzawa et al.
"Various Detecting Algorithms", Rev. 001, Nov., 1995 with English translation.

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