Overlay measurement technique using moire patterns

Details Overlay measurement technique using moire patterns Overlay measurement technique using moire patterns

1998-06-15

2000-11-21

Bowers, Charles

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

H01L 2176

Patent

active

061502316

ABSTRACT:
Misalignment between two masking steps used in the manufacture of semiconductive devices in a wafer is determined by having a special alignment pattern on each of two masks used in the process and forming images of the masks on the semiconductor devices with the images of the alignment patterns being superimposed over one another to form a Moire pattern. The Moire pattern is compared with other Moire patterns known to correspond to particular amounts of misalignment of the masks to see if it corresponds to an acceptable alignment.

REFERENCES:
patent: 3690881 (1972-09-01), King et al.
patent: 4568189 (1986-02-01), Bass et al.
patent: 5388517 (1995-02-01), Levien
Patent Abstracts of Japan, vol. 1995,No. 8, Sep. 29, 1995 & JP 02 120221(Oki Electric Ind. Co. Ltd.), May 12, 1995.
Patent Abstracts of Japan, vol. 014, No. 229, May 15,1990 & JP 02 060120(Mitsubishi Electric Corp.), Feb.28, 1990.
Patent Abstracts of Japan, vol. 015, No. 384, Sep. 27, 1991 & JP 03 154803 (Tosoh Corp.) Jul. 2, 1991.

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