Overlay mark, method for forming the same and application...

Details Overlay mark, method for forming the same and application... Overlay mark, method for forming the same and application...

2006-09-21

2008-10-07

Pham, Thanh V (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C438S401000, C438S462000, C438S042000, C438S424000, C438S429000, C438S430000, C438S700000, C438S701000

Reexamination Certificate

active

07432605

ABSTRACT:
An overlay mark for checking the alignment accuracy between a lower layer and a lithography process for defining an upper layer is described, including a part of the lower layer having two first x-directional trenches, two first y-directional trenches, two second x-directional trenches and two second y-directional trenches therein, and two x-directional and two y-directional photoresist bars thereover that are surrounded by the trenches and formed in the lithography process. When the lower layer is fully aligned with the lithography process, the intersection of the central line of the two first x-directional trenches and that of the two first y-directional trenches, the intersection of the central line of the two second x-directional trenches and that of the two second y-directional trenches and the intersection of the central line of the two x-directional photoresist lines and that of the two y-directional photoresist lines coincide with each other.

REFERENCES:
patent: 3969749 (1976-07-01), Bean
patent: 4172664 (1979-10-01), Charsky et al.
patent: 6184151 (2001-02-01), Adair et al.
patent: 2006/0118974 (2006-06-01), Kim et al.
patent: 2006/0138410 (2006-06-01), Lalbahadoersing et al.
patent: 2006/0151890 (2006-07-01), Smith et al.

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