Overlay mark arrangement for reducing overlay shift

Details Overlay mark arrangement for reducing overlay shift Overlay mark arrangement for reducing overlay shift

2011-05-31

2011-05-31

Coleman, W. David (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257SE23179, C382S151000

Reexamination Certificate

active

07952213

ABSTRACT:
An overlay mark arrangement for reducing the asymmetric profile and an overlay shift during an integrated circuit manufacturing process is disclosed. In one embodiment, the overlay mark arrangement may comprise a first mark, a second mark and a stress releasing means. The first mark is used to indicate the position of a lower layer, the second mark is used to indicate the position of an upper layer; and the stress releasing means is used to release the film stress induced by the upper layer. Unlike the conventional overlay mark arrangements, which will have a severe overlay mark shift due to the film stress, the asymmetric overlay mark profile can be improved by using multiple trenches around the overlay marks according to certain embodiments of the invention disclosed herein.

REFERENCES:
patent: 6801313 (2004-10-01), Yokota
patent: 7190824 (2007-03-01), Chen
patent: 7196429 (2007-03-01), Yen et al.
patent: 7449792 (2008-11-01), Yang et al.

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