Overlay mark

Details Overlay mark Overlay mark

2006-07-05

2008-12-02

Smoot, Stephen W (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257SE23179

Reexamination Certificate

active

07459798

ABSTRACT:
An overlay mark is provided. A first material layer is formed on a substrate, and then a first trench serving as a trench type outer mark is formed in the first material layer. The first trench is partially filled with the first deposition layer. A second material is formed over the first trench and the first deposition layer. A second trench is formed exposing the first deposition layer within the first trench. The second trench is partially filled with a second deposition layer forming a third trench. A third material layer is formed on the substrate to cover the second deposition layer and the second material layer. A step height is formed on the third deposition layer between the edge of the first trench and the center of the first trench. A raised feature serving as an inner mark is formed on the third deposition layer.

REFERENCES:
patent: 5858854 (1999-01-01), Tsai et al.
patent: 5889335 (1999-03-01), Kuroi et al.
patent: 6136662 (2000-10-01), Allman et al.
patent: 6153492 (2000-11-01), Wege et al.
patent: 6774452 (2004-08-01), Ramkumar et al.
patent: 7196429 (2007-03-01), Yen et al.
patent: 2003/0102576 (2003-06-01), Teramoto

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