Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression
Reexamination Certificate
2005-12-13
2005-12-13
Frejd, Russell (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Modeling by mathematical expression
C700S109000, C700S121000, C716S030000
Reexamination Certificate
active
06975974
ABSTRACT:
In the manufacturing of VLSI circuits, production of overlay is a critical step. To obtain a higher resolution and alignment accuracy in microlithographic process, overlay errors must be measured so that overlay errors can be reduced to a tolerable level. This invention provides an overlay error model and a sampling strategy. Utilizing the overlay model and sampling strategy, a device for measuring overlay errors is also designed.
REFERENCES:
patent: 4833621 (1989-05-01), Umatate
patent: 4918320 (1990-04-01), Hamasaki et al.
patent: 5448333 (1995-09-01), Iwamoto et al.
patent: 5498501 (1996-03-01), Shimoda et al.
patent: 5502311 (1996-03-01), Imai et al.
patent: 5805866 (1998-09-01), Magome et al.
patent: 6442496 (2002-08-01), Pasadyn et al.
patent: 6535774 (2003-03-01), Bode et al.
patent: 6556959 (2003-04-01), Miller et al.
Buller et al., Manufacturing Issues Related to RTP Induced Overlay Errors in a Global Alignment Stepper Technology, IEEE Transactions on Semiconductor Manufacturing, vol. 9, No. 1, Feb. 1996, p. 108-114.
Hebb et al., The Effect of Patterns on Thermal Stress During Rapid Thermal Processing of Silicon Wafers, IEEE Transactions on Semiconductor Manufacturing, vol. 11, No. 1, Feb. 1998, p. 99-107.
Preil et al., A New Approach to Correlating Overlay and Yield, SPIE Conference on Metrology, Inspection, and Process Control, for Microlithography XIII, vol. 3677, Mar. 1999, p. 208-16.
Shamoun et al., Assessment of Thermal Loading-Induced Distortions in Optical Photomasks Due to e-Beam Multipass Patterning, 42nd Int. Con. on Electron, Ion, and Photon Beam Tech/Nanofabrica-tion, American Vacuum Society, Nov./Dec. 1998, p. 3558-62.
Goodwin et al., Characterizing Overlay Registration of Concentric 5X and 1X Stepper Exposure Fields Using Interfield Data, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XI, vol. 3050, Mar. 1997, p. 407-17.
Chien et al., Sampling Strategy and Model to Measure and Compensate the Overlay Errors, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XV, vol. 4344, Feb./Mar. 2001, p. 245-56.
Hong et al., Interfield Sampling Method Dependency of Overlay and Global Alignment, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIV, vol. 3998, Feb./Mar. 2000, p. 856-62.
Arnold, Overlay Simulator for Wafer Steppers, SPIE vol. 922, Optical/Laser Microlithography, Mar. 1988, p. 94-105.
Chang Kuo-Hao
Chen Chih-Ping
Chien Chen-Fu
Lin Shun-Li
Frejd Russell
J. C. Patents
Macronix International Co. Ltd.
LandOfFree
Overlay error model, sampling strategy and associated... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Overlay error model, sampling strategy and associated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Overlay error model, sampling strategy and associated... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3511866