Overlay alignment metrology using diffraction gratings

Details Overlay alignment metrology using diffraction gratings Overlay alignment metrology using diffraction gratings

2002-02-12

2004-11-16

Smith, Zandra V. (Department: 2877)

Optics: measuring and testing

By alignment in lateral direction

With registration indicia

C356S400000

Reexamination Certificate

active

06819426

ABSTRACT:

TECHNICAL FIELD
This invention relates to measuring the pattern overlay alignment accuracy of a pair of patterned layers on a semiconductor wafer, possibly separated by one or more layers, made by two or more lithography steps during the manufacture of semiconductor devices.
BACKGROUND ART
Manufacturing semiconductor devices involves depositing and patterning several layers overlaying each other. For example, gate interconnects and gates of a CMOS integrated circuit have layers with different patterns, which are produced by different lithography stages. The tolerance of alignment of the patterns at each of these layers can be smaller than the width of the gate. At the time of this writing, the smallest linewidth that can be mass produced is 130 nm. The state of the art mean +3&sgr; alignment accuracy is 30 nm (Nikon KrF Step-and-Repeat Scanning System NSR-S205C, July 2000).
Overlay metrology is the art of checking the quality of alignment after lithography. Overlay error is defined as the offset between two patterned layers from their ideal relative position. Overlay error is a vector quantity with two components in the plane of the wafer. Perfect overlay and zero overlay error are used synonymously. Depending on the context, overlay error may signify one of the components or the magnitude of the vector.
Overlay metrology saves subsequent process steps that would be built on a faulty foundation in case of an alignment error. Overlay metrology provides the information that is necessary to correct the alignment of the stepper-scanner and thereby minimize overlay error on subsequent wafers. Moreover, overlay errors detected on a given wafer after exposing and developing the photoresist can be corrected by removing the photoresist and repeating the lithography step on a corrected stepper-scanner. If the measured error is minor, parameters for subsequent steps of the lithography process could be adjusted based on the overlay metrology to avoid excursions. If overlay error is measured subsequently, e.g., after the etch step that typically follows develop, it can be used to “scrap” severely mis-processed wafers, or to adjust process equipment for better performance on subsequent wafers.
Prior overlay metrology methods use built-in test patterns etched or otherwise formed into or on the various layers during the same plurality of lithography steps that form the patterns for circuit elements on the wafer. One typical pattern, called “box-in-box” consists of two concentric squares, formed on a lower and an upper layer, respectively. “Bar-in-bar” is a similar pattern with just the edges of the “boxes” demarcated, and broken into disjoint line segments, as shown in FIG.
1
. The outer bars
2
are associated with one layer and the inner bars
4
with another. Typically one is the upper pattern and the other is the lower pattern, e.g., outer bars
2
on a lower layer, and inner bars
4
on the top. However, with advanced processes the topographies are complex and not truly planar so the designations “upper” and “lower” are ambiguous. Typically they correspond to earlier and later in the process. There are other patterns used for overlay metrology. The squares or bars are formed by lithographic and other processes used to make planar structures, e.g., chemical-mechanical planarization (CMP). Currently, the patterns for the boxes or bars are stored on lithography masks and projected onto the wafer. Other methods for putting the patterns on the wafer are possible, e.g., direct electron beam writing from computer memory, etc.
In one form of the prior art, a high performance microscope imaging system combined with image processing software estimates overlay error for the two layers. The image processing software uses the intensity of light at a multitude of pixels. Obtaining the overlay error accurately requires a high quality imaging system and means of focusing it. Some of this prior art is reviewed by the article “Semiconductor Pattern Overlay”, by Neal T. Sullivan, Handbook of Critical Dimension Metrology and Process Control: Proceedings of Conference held 28-29 Sep. 1993, Monterey, Calif., Kevin M. Monahan, ed., SPIE Optical Engineering Press, vol. CR52, pp. 160-188. A. Starikov, D. J. Coleman, P. J. Larson, A. D. Lapata, W. A. Muth, in “Accuracy of Overlay Measurements: Tool and Mark Asymmetry Effects,” Optical Engineering, vol. 31, 1992, p. 1298, teach measuring overlay at one orientation, rotating the wafer by 180°, measuring overlay again and attributing the difference to tool errors and overlay mark asymmetry.
One requirement for the optical system is very stable positioning of the optical system with respect to the sample. Relative vibration would blur the image and degrade the performance. This is a difficult requirement to meet for overlay metrology systems that are integrated into a process tool, like a lithography track. The tool causes potentially large accelerations (vibrations), e.g., due to high acceleration wafer handlers. The tight space requirements for integration preclude bulky isolation strategies.
The imaging-based overlay measurement precision can be two orders of magnitude smaller than the wavelength of the light used to image the target patterns of concentric boxes or bars. At such small length scales, the image does not have well determined edges because of diffraction. The determination of the edge, and therefore the overlay measurement, is affected by any factor that changes the diffraction pattern. Chemical-mechanical planarization (CMP) is a commonly used technique used to planarize the wafer surface at intermediate process steps before depositing more material. CMP can render the profile of the trenches or lines that make up the overlay measurement targets asymmetric.
FIG. 2
illustrates an overlay target feature
2
which is a trench filled with metal. Surface
3
is planarized by CMP. The CMP process erodes the surface of the overlay mark
2
in an asymmetric manner. The overlay target
2
is compared subsequently to target feature
4
in the overlying layer, which could be, e.g., photoresist of the next lithography step. The asymmetry in target feature
2
changes the diffraction pattern, thus potentially causing an overlay measurement error.
In U.S. Pat. No. 4,757,207, Chappelow, et al. teach obtaining the quantitative value of the overlay offset from the reflectance of targets that consists of identical line gratings that are overlaid upon each other on a planar substrate. Each period of the target consists of four types of film stacks: lines of the lower grating overlapping with the spaces of the upper grating, spaces of the lower grating overlapping with the lines of the upper grating, lines of the lower and upper gratings overlapping, spaces of the lower and upper gratings overlapping. Chappelow et al, approximate the reflectance of the overlapping gratings as the average of the reflectances of the four film stacks weighted by their area-fractions. This approximation, which neglects diffraction, has some validity when the lines and spaces are larger than largest wavelength of the reflectometer. The reflectance of each of the four film stacks is measured at a so called macro-site close to the overlay target. Each macro-site has a uniform film stack over a region that is larger than the measurement spot of the reflectometer. A limitation of U.S. Pat. No. 4,757,207 is that spatial variations in the film thickness that are caused by CMP and resist loss during lithography will cause erroneous overlay measurements. Another limitation of U.S. Pat. No. 4,757,207 is that reflectance is measured at eight sites in one overlay metrology target, which increases the size of the target and decreases the throughput of the measurement. Another limitation of U.S. Pat. No. 4,757,207 is that the lines and spaces need to be large compared to the wavelength, but small compared to the measurement spot which limits the accuracy and precision of the measurement. Another limitation of U.S. Pat. No. 4,757,207 is that the light intensity is measured by a single photodiode.

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