Overlapped multiple-bit scanning multiplication system with band

Details Overlapped multiple-bit scanning multiplication system with band Overlapped multiple-bit scanning multiplication system with band

1987-11-03

1990-04-17

LaRoche, Eugene R.

Boots, shoes, and leggings

364757, G06F 752

Patent

active

049186396

ABSTRACT:
A multi-bit overlapped scanning multiplication system assembles modified partial products in a reduced, non-rectangular banded matrix. The rows of the matrix except for the first and last, are extended with bands of encoded extensions of limited length at the right and left ends of the partial product terms. The width of the significant bits of each partial product term is equal to q-1+S-2, where q is the width of the significant bits plus sign of the multiplicand and S is the number of bits which are overlapped scanned. Each partial product term is shifted S-1 bits from adjacent terms and is banded by encoded extensions to the terms. S-1 bits of encode are placed to the right of every terms except the last, the encode being based on the sign of the next partial product term; and S-1 bits of encoded sign extension are placed to the left of every term except the first, which has no sign extension, and last, to the left of which is placed an S bit encode. The bits of negative partial product terms are inverted, and a "hot 1" is encoded in the right extension in the previous row. The first bit of the multiplier is forced to zero so that the first partial product term is always positive or zero. Carry save adder trees are used to reduce each column of the matrix to two terms. When inputs to a carry save adder are known, the logic of the carry save adder is simplified to save chip space.

REFERENCES:
patent: 4748582 (1988-05-01), New et al.
"Multiply-Addition--An Ultra High Performance Dataflow", IBM Technical Disclosure Bulletin, vol. 30, No. 3, Aug. 1987, pp. 982-987.

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